# Verilog generate for always blocks in myhdl

**URL:** <https://discourse.myhdl.org/t/verilog-generate-for-always-blocks-in-myhdl/246>\
**Category:** Support\
**Created:** [January 19, 2018, 3:34pm UTC](https://discourse.myhdl.org/t/verilog-generate-for-always-blocks-in-myhdl/246 "2018-01-19T15:34:27Z")\
**Posts on this page:** 5\
**Page:** 1

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**Author:** ![aurang](https://avatars.discourse-cdn.com/v4/letter/a/9fc29f/32.png) [@aurang](https://discourse.myhdl.org/u/aurang)\
**Post date:** [January 19, 2018, 3:34pm UTC](https://discourse.myhdl.org/t/verilog-generate-for-always-blocks-in-myhdl/246/1 "2018-01-19T15:34:27Z")

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Hi,

is it possible to write code in myhdl which serves the same purpose as “generate” keyword in Verilog for always blocks.  
Does the converted code then represents the correct hardware behavior.  
I did not find any example in my search.

Thanks!  
Aurang

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**Author:** ![cfelton](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/cfelton/32/3_2.png) [@cfelton](https://discourse.myhdl.org/u/cfelton)\
**Post date:** [January 19, 2018, 9:32pm UTC](https://discourse.myhdl.org/t/verilog-generate-for-always-blocks-in-myhdl/246/2 "2018-01-19T21:32:26Z")

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All the Python code outside of a myhdl generator is _elaboration_ code, similar to V\* generate statements. But the Python/myhdl is more powerful, you have all the features of Python in the elaboration phase (code outside of `myhdl.instance`, `myhdl.always`, `myhdl.always_seq`, and `myhdl.always_comb`).

Regards,  
Chris

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**Author:** ![cfelton](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/cfelton/32/3_2.png) [@cfelton](https://discourse.myhdl.org/u/cfelton)\
**Post date:** [January 19, 2018, 9:36pm UTC](https://discourse.myhdl.org/t/verilog-generate-for-always-blocks-in-myhdl/246/3 "2018-01-19T21:36:52Z")

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Here is an example in the manual: [http://docs.myhdl.org/en/stable/manual/structure.html#inferring-the-list-of-instances](http://docs.myhdl.org/en/stable/manual/structure.html#inferring-the-list-of-instances)

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<div class="post-metadata">

**Author:** ![aurang](https://avatars.discourse-cdn.com/v4/letter/a/9fc29f/32.png) [@aurang](https://discourse.myhdl.org/u/aurang)\
**Post date:** [January 22, 2018, 11:44am UTC](https://discourse.myhdl.org/t/verilog-generate-for-always-blocks-in-myhdl/246/4 "2018-01-22T11:44:14Z")

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Thanks for your quick clarification.

Regards,  
Aurang

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<div class="post-metadata">

**Author:** ![cfelton](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/cfelton/32/3_2.png) [@cfelton](https://discourse.myhdl.org/u/cfelton)\
**Post date:** [January 22, 2018, 7:16pm UTC](https://discourse.myhdl.org/t/verilog-generate-for-always-blocks-in-myhdl/246/5 "2018-01-22T19:16:57Z")

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Let us know if you have more questions or need more examples.