# VHDL block equivalent in MyHDL?

**URL:** <https://discourse.myhdl.org/t/vhdl-block-equivalent-in-myhdl/222>\
**Category:** Support\
**Created:** [September 22, 2017, 7:22am UTC](https://discourse.myhdl.org/t/vhdl-block-equivalent-in-myhdl/222 "2017-09-22T07:22:01Z")\
**Posts on this page:** 13\
**Page:** 1

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**Author:** ![DrPi](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/drpi/32/36_2.png) [@DrPi](https://discourse.myhdl.org/u/DrPi)\
**Post date:** [September 22, 2017, 7:22am UTC](https://discourse.myhdl.org/t/vhdl-block-equivalent-in-myhdl/222/1 "2017-09-22T07:22:01Z")

</div>

Hi,

In VHDL, I heavily use block statements to manage locals signals.  
For example :

```auto
signal PrescalerTrig : std_logic := '0';
...
    b_prescaler :
    block
    signal Counter : integer range 0 to 255 := 0;
    
    begin
        process (Clk)
        begin
            if rising_edge(i_Clk) then
                PrescalerTrig <= '0';
                if Counter = CLK_DIVIDER then
                    Counter <= 0;
                    PrescalerTrig <= '1';
                else
                    Counter <= Counter + 1;
                end if;
            end if;
        end process;
    end block;

    b_tx :
    block
    signal Counter : integer range 0 to 16 := 0;
    
    begin
        process (Clk)
        begin
            if rising_edge(i_Clk) then
                if PrescalerTrig = '1' then
                    Counter <= Counter + 1;
                .
                .
                .
                end if;
            end if;
        end process;
    end block;

```

Using local signals makes the code much more readable and less prone to errors.

Is there an equivalent writing in MyHDL ?

---

<div class="post-metadata">

**Author:** ![josyb](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/josyb/32/5_2.png) [@josyb](https://discourse.myhdl.org/u/josyb)\
**Post date:** [September 22, 2017, 8:22am UTC](https://discourse.myhdl.org/t/vhdl-block-equivalent-in-myhdl/222/2 "2017-09-22T08:22:53Z")

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MyHDL isn’t meant to produce _maintainable_ V\* code. Of course it helps that the generated code looks nice and readable. IMO the _name prefixing_ produces acceptable _traceable_ names.  
The closest you can get is using local variables in MyHDL, it will produce a local variable in VHDL.

---

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**Author:** ![DrPi](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/drpi/32/36_2.png) [@DrPi](https://discourse.myhdl.org/u/DrPi)\
**Post date:** [September 22, 2017, 8:32am UTC](https://discourse.myhdl.org/t/vhdl-block-equivalent-in-myhdl/222/3 "2017-09-22T08:32:48Z")

</div>

The purpose is not to “produce maintainable V\* code”.  
VHDL ‘block’ statements are useful for readability and limit design errors.  
Name prefixing is a solution. A bad solution to my point of view.

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<div class="post-metadata">

**Author:** ![josyb](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/josyb/32/5_2.png) [@josyb](https://discourse.myhdl.org/u/josyb)\
**Post date:** [September 22, 2017, 9:44am UTC](https://discourse.myhdl.org/t/vhdl-block-equivalent-in-myhdl/222/4 "2017-09-22T09:44:58Z")

</div>

_The purpose is not to “produce maintainable V_ code”.\*  
Then nothing else matters?  
You simulate in MyHDL (and possibly cosimulate), convert and use. If you really have to _debug_ at the VHDL level, the generated names are good enough, certainly not _bad_.  
I adopted a naming convention which produces very traceable names: CamelCase for ports and lowercase without underscores for signals and modules/functions, UPPER\_CASE for constants.This generates signals like: `sync_syncs2_counter_IsZero` where you can think of the ‘\_’ representing the ‘. as we use in Python.’

---

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**Author:** ![DrPi](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/drpi/32/36_2.png) [@DrPi](https://discourse.myhdl.org/u/DrPi)\
**Post date:** [September 22, 2017, 11:25am UTC](https://discourse.myhdl.org/t/vhdl-block-equivalent-in-myhdl/222/5 "2017-09-22T11:25:16Z")

</div>

There might be some confusion here. My goal is to write better MyHDL code. Nothing to do with VHDL or Verilog.  
In my original post, I show a VHDL example where 2 blocks use a counter simply named Counter. This is clear, each Counter is in its own scope.  
In MyHDL, when coding such functionality, I have to create 2 signals with different names because they are in the same scope. This is less readable and can lead to errors. You know, ctrl+c and ctrl+v…

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<div class="post-metadata">

**Author:** ![josyb](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/josyb/32/5_2.png) [@josyb](https://discourse.myhdl.org/u/josyb)\
**Post date:** [September 22, 2017, 12:40pm UTC](https://discourse.myhdl.org/t/vhdl-block-equivalent-in-myhdl/222/6 "2017-09-22T12:40:11Z")

</div>

For the typical case of a counter use a MyHDL variable. I didn’t have a good example ready; as I re-use a counter object (and the prefixing takes care of the naming).

I then made one up:

````python
def counter(Clk, Q):
    CLK_DIVIDER = 256 - 1
    prescalertrig = Signal(bool(0))

    counter = intbv(0)[8:]

    @always_seq(Clk.posedge, reset=None)
    def prescaler():
        ''' Prescaler '''
    
        prescalertrig.next = 0
        if counter == CLK_DIVIDER:
            counter[:] = 0
            prescalertrig.next = 1
        else:
            counter[:] = counter + 1
       
    counter = intbv(0)[4:] # yes we are re-using the 'name' only, not the 'object'

    @always_seq(Clk.posedge, reset=None)
    def thecounter():
        ''' The Counter '''
    
        Q.next = counter
        if prescalertrig:
            if counter == 15:
                counter[:] = 0
            else:
                counter[:] = counter + 1
                
    return prescaler, thecounter```

producing this VHDL:
```VHDL
	signal prescalertrig : std_logic := '0';

begin

	-- Prescaler 
	prescaler : process(Clk) is
		variable counter : unsigned(3 downto 0);
	begin
		if rising_edge(Clk) then
			prescalertrig <= '0';
			if (counter = 255) then
				counter := to_unsigned(0, 4);
				prescalertrig <= '1';
			else
				counter := (counter + 1);
			end if;
		end if;
	end process prescaler;

	-- The Counter 
	thecounter : process(Clk) is
		variable counter : unsigned(3 downto 0);
	begin
		if rising_edge(Clk) then
			Q <= counter;
			if bool(prescalertrig) then
				if (counter = 15) then
					counter := to_unsigned(0, 4);
				else
					counter := (counter + 1);
				end if;
			end if;
		end if;
	end process thecounter;

````

Variables can be a bit tricky in VHDL though, so we may want to read up on this. There probably is an error in the code …

---

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**Author:** ![DrPi](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/drpi/32/36_2.png) [@DrPi](https://discourse.myhdl.org/u/DrPi)\
**Post date:** [September 22, 2017, 1:15pm UTC](https://discourse.myhdl.org/t/vhdl-block-equivalent-in-myhdl/222/7 "2017-09-22T13:15:02Z")

</div>

Interesting… but very misleading.  
I avoid using variables as much as possible. Even in VHDL.

Just thinking that maybe one can declare signals in “process” functions…

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**Author:** ![josyb](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/josyb/32/5_2.png) [@josyb](https://discourse.myhdl.org/u/josyb)\
**Post date:** [September 22, 2017, 1:28pm UTC](https://discourse.myhdl.org/t/vhdl-block-equivalent-in-myhdl/222/8 "2017-09-22T13:28:03Z")

</div>

Why _very misleading_? Will you humour me and explain?

I too use variables very seldom.

If you declare the variable inside the @always\_seq it will be initialised every clock (which we sometimes may want to)

---

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**Author:** ![DrPi](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/drpi/32/36_2.png) [@DrPi](https://discourse.myhdl.org/u/DrPi)\
**Post date:** [September 22, 2017, 1:43pm UTC](https://discourse.myhdl.org/t/vhdl-block-equivalent-in-myhdl/222/9 "2017-09-22T13:43:00Z")

</div>

> [@josyb](#):
>
> Why very misleading? Will you humour me and explain?

In the same scope, two objects are manipulated using the same name.  
In your example, imagine I miss the second instantiation (because it is late and I am tired), every thing will be ok from MyHDL point of view. But the system will not work as expected. Bugs like this are very hard to find because you don’t search for them.  
Also, reading this code can lead to misunderstanding if you overlook the second instantiation.  
With much more complex code, this is a real problem. From my point of view.

> [@josyb](#):
>
> If you declare the variable inside the @always\_seq it will be initialised every clock (which we sometimes may want to)

Sure.

I tried to instanciate signals in “process” functions but this gives an error. Not surprising.

---

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**Author:** ![josyb](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/josyb/32/5_2.png) [@josyb](https://discourse.myhdl.org/u/josyb)\
**Post date:** [September 22, 2017, 2:09pm UTC](https://discourse.myhdl.org/t/vhdl-block-equivalent-in-myhdl/222/10 "2017-09-22T14:09:26Z")

</div>

Point taken. It is less evident and it may as well not work …

IMO I feel this feature would be too much work, and _not_ worth the effort.  
Using distinct names should not pose a real problem.  
Second you can re-factor the @always\_seq processes into separate functions/classes and MyHDL will take care of the naming. And it will reduce the verbosity of the _top_ function/module, improving the readability.

---

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**Author:** ![DrPi](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/drpi/32/36_2.png) [@DrPi](https://discourse.myhdl.org/u/DrPi)\
**Post date:** [September 22, 2017, 2:26pm UTC](https://discourse.myhdl.org/t/vhdl-block-equivalent-in-myhdl/222/11 "2017-09-22T14:26:42Z")

</div>

> [@josyb](#):
>
> IMO I feel this feature would be too much work, and worth the effort.

My goal was not to request a new feature. I just wanted to know if other users have found a smarter way of coding.

> [@josyb](#):
>
> Second you can re-factor the @always\_seq processes into separate functions/classes and MyHDL will take care of the naming. And it will reduce the verbosity of the top function/module, improving the readability.

I already though about it but I concluded that it would make the code less readable. This is because I though I have to declare the functions in the main function body. But I don’t have to. Declaring the functions outside the main function might be the solution.

---

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**Author:** ![josyb](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/josyb/32/5_2.png) [@josyb](https://discourse.myhdl.org/u/josyb)\
**Post date:** [September 22, 2017, 3:27pm UTC](https://discourse.myhdl.org/t/vhdl-block-equivalent-in-myhdl/222/12 "2017-09-22T15:27:04Z")

</div>

> [@DrPi](#):
>
> My goal was not to request a new feature. I just wanted to know if other users have found a smarter way of coding.

I feel we should try to enhance MyHDL as much as possible, but there is only so much time,

> [@DrPi](#):
>
> Declaring the functions outside the main function might be the solution.

Or declare them in a separate module and import them. This will lead to re-usability in other projects?

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<div class="post-metadata">

**Author:** ![DrPi](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/drpi/32/36_2.png) [@DrPi](https://discourse.myhdl.org/u/DrPi)\
**Post date:** [September 25, 2017, 7:02am UTC](https://discourse.myhdl.org/t/vhdl-block-equivalent-in-myhdl/222/13 "2017-09-25T07:02:06Z")

</div>

> [@josyb](#):
>
> I feel we should try to enhance MyHDL as much as possible, but there is only so much time,

Sure.

> [@josyb](#):
>
> Or declare them in a separate module and import them. This will lead to re-usability in other projects?

I have already completed 3 designs using MyHDL (Target is a Lattice MACHXO2).  
Of course I use many modules for various functionalities : I2C slave, IRQ management, registers management, edge detector, GPIO…  
Some modules are more complex than others and are formed of “submodules”.  
For example, a RS2232 transmitter. This transmitter needs a prescaler to manage the transmission speed and a core transmitter (using prescaler output). I don’t want to create a module for the prescaler and a module for the core transmitter. I want just one module containing all the logic. The prescaler is specific to this module, so is the core transmitter. Defining a function for the prescaler and another one for the core transmitter in the module is ok for me.  
As you said, it has the advantage of a simpler, more readable, top module.