# VHDL constant value overflow

**URL:** <https://discourse.myhdl.org/t/vhdl-constant-value-overflow/326>\
**Category:** Bug\
**Created:** [August 29, 2018, 12:35pm UTC](https://discourse.myhdl.org/t/vhdl-constant-value-overflow/326 "2018-08-29T12:35:11Z")\
**Posts on this page:** 1\
**Showing post:** 9

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**Author:** ![mhavu](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/mhavu/32/86_2.png) [@mhavu](https://discourse.myhdl.org/u/mhavu)\
**Post date:** [August 31, 2018, 12:21pm UTC](https://discourse.myhdl.org/t/vhdl-constant-value-overflow/326/9 "2018-08-31T12:21:35Z")

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> [@DrPi](#):
>
> We already spoke about this before in other threads. I think we need constants in MyHDL.  
> I already started to code such a functionality but only for VHDL, not for verilog.

Do you mean [this one](http://discourse.myhdl.org/t/matching-a-signal-against-a-bitvector/274/8)? What do you guys think about adding generics support in the constant type? In my opinion, the constructor for the constant type could have a named parameter with default value `parameter=False`. If `parameter` were set to `True`, a generic would be generated instead of a constant.

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