MyHDL Discourse

Inverting a signal passed into a module


#1

When I use the form

ff_1 = dffe(reset, clock, d, q, ena)

I get the expected results. But when I do this

ff_1 = dffe(reset, clock, d, q, not ena)

or

ff_1 = dffe(reset, clock, d, q, not(ena))

I get

ToVerilogWarning: Signal is driven but not read: ena

What is the correct form for passing in an inverted signal?


#2

This is something that doesn’t work; you have to pass a Signal proper. the not evaluates its argument (ena in this case). MyHDL will only evaluate that line once; it is the returned generators that do the simulation work, and that are the ones that get converted.

The workaround:

ena_n = Signal(bool(0))

@always_comb
def mknot():
    ena_n.next = not ena


ff_1 = dffe(reset, clock, d, q, ena_n)

. . .

return mknot, ff_1, ...

#3

Thank you, @josyb! Makes sense now. I guess we’re all hoping that it might work someday?