MyHDL

Evaluating bools implicitly/explicitly

I have a design with the following:

@block
def x(...):
    write = Signal(False)
    ...
    @always_seq(clock.posedge, reset=reset)
    def logic():
        ...
        if write == True:
        ...

and I get this error on conversion:

AttributeError: 'Constant' object has no attribute 'signed'

If I change the last line of the above code to:

if write:

conversion is successful. I’m puzzled. I hope I haven’t oversimplified this. I’ve been searching for hours for the reason but have not found it yet.

I’ve not seen signals declared like this, more usually like these here:

http://docs.myhdl.org/en/stable/manual/structure.html#introduction

Jan