When I use the form
ff_1 = dffe(reset, clock, d, q, ena)
I get the expected results. But when I do this
ff_1 = dffe(reset, clock, d, q, not ena)
ff_1 = dffe(reset, clock, d, q, not(ena))
ToVerilogWarning: Signal is driven but not read: ena
What is the correct form for passing in an inverted signal?
This is something that doesn’t work; you have to pass a Signal proper. the
not evaluates its argument (ena in this case). MyHDL will only evaluate that line once; it is the returned generators that do the simulation work, and that are the ones that get converted.
ena_n = Signal(bool(0))
ena_n.next = not ena
ff_1 = dffe(reset, clock, d, q, ena_n)
. . .
return mknot, ff_1, ...
Thank you, @josyb! Makes sense now. I guess we’re all hoping that it might work someday?