Support

Bug The category is applied to support questions that could be bugs (and not limitations). Tests should be created for all topics with the Bug category and a pull-request generated. FAQ This category addresses frequently asked questions [FAQ], see also the myhdl.org FAQ page

Topic	Replies	Views	Activity
About the Support category Support	0	1024	May 15, 2016
Conditional conversion tricks? Support	3	160	July 14, 2025
Converting enum code (integer) to EnumItem Support	9	232	April 15, 2025
New to MyHDL - how should I connect outputs to inputs properly? Support	3	183	January 24, 2025
Cosimulation output port conflict (X) Support	2	120	October 4, 2024
Cosimulation with waveform dump Support	2	1192	October 1, 2024
Managing scattered codebase Support	0	72	September 30, 2024
VHDL constant value overflow Bug	16	4106	July 24, 2024
How to get the latest Version of myhdl 2 Support	4	683	February 26, 2023
How to get latest version of myhdl? Support	12	740	December 11, 2022
Pull Request Cleanup Support	1	455	December 8, 2022
myhdl.AlwaysCombError: sensitivity list is empty Support	1	581	November 9, 2022
Sub module Verilog synthesis error Support	3	669	June 17, 2022
Sign extend bits Support	2	803	May 10, 2022
Multiple @always_comb needed - why? Support	35	1348	April 26, 2022
Signed error with lshift Support	3	527	April 24, 2022
Sanity check: Ps/2 Keyboard on an fpga Support	2	653	April 21, 2022
Preserve hierarchy Support	8	1409	April 19, 2022
I am implementing single cycle processor, RV32I ... i am facing issues in top module.. file named as " core.py " Support	1	651	December 9, 2021
I am having issue, when i am converting myhdl to verilog it gives me error on list indexing Bug	0	511	November 29, 2021
Is MyHDL a good choice to create BFMs? FAQ	6	923	November 16, 2021
Shadow Signals are not updating Support	2	570	September 20, 2021
Natural method for expressing horizontal microcode? Support	4	609	August 23, 2021
Modelling wired-or (wired-and) bus behaviour Support	4	637	August 23, 2021
Result of multiplication is zero. Not so in simulation FAQ	9	811	June 13, 2021
Myhdl: how to set pin to 'high impedance' FAQ	1	659	May 17, 2021
Initial values, memories, and Yosys Support	11	3032	April 16, 2021
How to avoid derived clock domains (i.e. ripple counter) FAQ	6	719	March 16, 2021
How to infer to unique case Support	1	502	March 12, 2021
Design functions when the clock is inverted Support	2	527	February 18, 2021