Support

Bug The category is applied to support questions that could be bugs (and not limitations). Tests should be created for all topics with the Bug category and a pull-request generated. FAQ This category addresses frequently asked questions [FAQ], see also the myhdl.org FAQ page

Topic	Replies	Views	Activity
About the Support category Support	0	606	May 15, 2016
Type mismatch with earlier assignment: FAQ	6	6	January 26, 2021
AssertionError: Unexpected callable Support	8	28	January 6, 2021
Myhdl signed assignment fails at runtime Support	4	28	December 23, 2020
Use VHDL library Support	3	141	July 5, 2020
Initial values, memories, and Yosys Support	9	638	April 7, 2020
List of signals as a port is not supported : mem Support	1	160	March 26, 2020
Is implementing a classification algorithm possible w/ MyHDL? Support	1	172	March 25, 2020
How to do signed operations on intbv Support	3	187	March 18, 2020
How can I implement this? Support	2	206	March 3, 2020
Another MyHDL VHDL conversion bug Bug	13	381	October 17, 2019
Mutiple traces/simulations in one run Support	4	300	October 13, 2019
How can I use lists of signals and still convert to verilog Support	12	453	September 18, 2019
Conversion problem with shadow signal Support	8	282	September 3, 2019
Unexpected signal name in converted VHDL Support	4	314	August 1, 2019
How to dynamically infer ports? Support	6	329	August 1, 2019
Large memory consumption Support	13	544	May 14, 2019
Preserve hierarchy Support	5	370	May 11, 2019
Vendor specific instance simulation Support	1	319	April 19, 2019
Conversion naming issue Support	8	356	April 5, 2019
Verilog conversion to write results to a file? Support	12	386	April 4, 2019
Don't care / unknown Support	4	333	March 28, 2019
Function not converting, but deflated code does Support	8	326	March 23, 2019
How to simulate for the ROM type design Support	17	644	March 12, 2019
'tuple' object has no attribute 'config_sim' Support	1	363	February 25, 2019
Changing testbench inputs during a simulation Support	8	361	February 13, 2019
Instantiating FPGA components Support	7	905	February 2, 2019
Combinational tree like accumulatioin Support	6	436	December 10, 2018
Cosimulation myhdl.vpi search path Support	2	1334	November 8, 2018
VHDL constant value overflow Bug	15	1487	November 5, 2018