Support

Bug The category is applied to support questions that could be bugs (and not limitations). Tests should be created for all topics with the Bug category and a pull-request generated. FAQ This category addresses frequently asked questions [FAQ], see also the myhdl.org FAQ page

Topic	Replies	Views	Activity
About the Support category Support	0	646	May 15, 2016
Result of multiplication is zero. Not so in simulation FAQ	9	104	June 13, 2021
Myhdl: how to set pin to 'high impedance' FAQ	1	54	May 17, 2021
Initial values, memories, and Yosys Support	11	899	April 16, 2021
How to avoid derived clock domains (i.e. ripple counter) FAQ	6	78	March 16, 2021
How to infer to unique case Support	1	61	March 12, 2021
Design functions when the clock is inverted Support	2	62	February 18, 2021
Using lists of signals in myhdl Support	2	93	February 10, 2021
Type mismatch with earlier assignment: FAQ	15	113	February 5, 2021
AssertionError: Unexpected callable Support	8	117	January 6, 2021
Myhdl signed assignment fails at runtime Support	4	92	December 23, 2020
Use VHDL library Support	3	203	July 5, 2020
List of signals as a port is not supported : mem Support	1	231	March 26, 2020
Is implementing a classification algorithm possible w/ MyHDL? Support	1	232	March 25, 2020
How to do signed operations on intbv Support	3	249	March 18, 2020
How can I implement this? Support	2	268	March 3, 2020
Another MyHDL VHDL conversion bug Bug	13	462	October 17, 2019
Mutiple traces/simulations in one run Support	4	388	October 13, 2019
How can I use lists of signals and still convert to verilog Support	12	573	September 18, 2019
Conversion problem with shadow signal Support	8	342	September 3, 2019
Unexpected signal name in converted VHDL Support	4	383	August 1, 2019
How to dynamically infer ports? Support	6	405	August 1, 2019
Large memory consumption Support	13	638	May 14, 2019
Preserve hierarchy Support	5	432	May 11, 2019
Vendor specific instance simulation Support	1	375	April 19, 2019
Conversion naming issue Support	8	457	April 5, 2019
Verilog conversion to write results to a file? Support	12	466	April 4, 2019
Don't care / unknown Support	4	435	March 28, 2019
Function not converting, but deflated code does Support	8	390	March 23, 2019
How to simulate for the ROM type design Support	17	794	March 12, 2019