Support

FAQ This category addresses frequently asked questions [FAQ], see also the myhdl.org FAQ page Bug The category is applied to support questions that could be bugs (and not limitations). Tests should be created for all topics with the Bug category and a pull-request generated.

Topic	Replies	Views	Activity
About the Support category Support	0	999	May 15, 2016
Converting enum code (integer) to EnumItem Support	9	34	April 15, 2025
New to MyHDL - how should I connect outputs to inputs properly? Support	3	33	January 24, 2025
Cosimulation output port conflict (X) Support	2	36	October 4, 2024
Cosimulation with waveform dump Support	2	1094	October 1, 2024
Managing scattered codebase Support	0	10	September 30, 2024
VHDL constant value overflow Bug	16	3750	July 24, 2024
How to get the latest Version of myhdl 2 Support	4	508	February 26, 2023
How to get latest version of myhdl? Support	12	522	December 11, 2022
Pull Request Cleanup Support	1	343	December 8, 2022
myhdl.AlwaysCombError: sensitivity list is empty Support	1	497	November 9, 2022
Sub module Verilog synthesis error Support	3	530	June 17, 2022
Sign extend bits Support	2	638	May 10, 2022
Multiple @always_comb needed - why? Support	35	793	April 26, 2022
Signed error with lshift Support	3	436	April 24, 2022
Sanity check: Ps/2 Keyboard on an fpga Support	2	554	April 21, 2022
Preserve hierarchy Support	8	1155	April 19, 2022
I am implementing single cycle processor, RV32I ... i am facing issues in top module.. file named as " core.py " Support	1	560	December 9, 2021
I am having issue, when i am converting myhdl to verilog it gives me error on list indexing Bug	0	471	November 29, 2021
Is MyHDL a good choice to create BFMs? FAQ	6	747	November 16, 2021
Shadow Signals are not updating Support	2	508	September 20, 2021
Natural method for expressing horizontal microcode? Support	4	529	August 23, 2021
Modelling wired-or (wired-and) bus behaviour Support	4	539	August 23, 2021
Result of multiplication is zero. Not so in simulation FAQ	9	613	June 13, 2021
Myhdl: how to set pin to 'high impedance' FAQ	1	564	May 17, 2021
Initial values, memories, and Yosys Support	11	2709	April 16, 2021
How to avoid derived clock domains (i.e. ripple counter) FAQ	6	582	March 16, 2021
How to infer to unique case Support	1	455	March 12, 2021
Design functions when the clock is inverted Support	2	466	February 18, 2021
Using lists of signals in myhdl Support	2	543	February 10, 2021