Support

FAQ This category addresses frequently asked questions [FAQ], see also the myhdl.org FAQ page Bug The category is applied to support questions that could be bugs (and not limitations). Tests should be created for all topics with the Bug category and a pull-request generated.

Topic	Replies	Views	Activity
About the Support category Support	0	996	May 15, 2016
VHDL constant value overflow Bug	16	3607	July 24, 2024
How to get the latest Version of myhdl 2 Support	4	493	February 26, 2023
How to get latest version of myhdl? Support	12	506	December 11, 2022
Pull Request Cleanup Support	1	339	December 8, 2022
myhdl.AlwaysCombError: sensitivity list is empty Support	1	487	November 9, 2022
Sub module Verilog synthesis error Support	3	507	June 17, 2022
Sign extend bits Support	2	598	May 10, 2022
Multiple @always_comb needed - why? Support	35	772	April 26, 2022
Signed error with lshift Support	3	433	April 24, 2022
Sanity check: Ps/2 Keyboard on an fpga Support	2	531	April 21, 2022
Preserve hierarchy Support	8	1131	April 19, 2022
I am implementing single cycle processor, RV32I ... i am facing issues in top module.. file named as " core.py " Support	1	550	December 9, 2021
I am having issue, when i am converting myhdl to verilog it gives me error on list indexing Bug	0	466	November 29, 2021
Is MyHDL a good choice to create BFMs? FAQ	6	713	November 16, 2021
Shadow Signals are not updating Support	2	499	September 20, 2021
Natural method for expressing horizontal microcode? Support	4	526	August 23, 2021
Modelling wired-or (wired-and) bus behaviour Support	4	534	August 23, 2021
Result of multiplication is zero. Not so in simulation FAQ	9	605	June 13, 2021
Myhdl: how to set pin to 'high impedance' FAQ	1	559	May 17, 2021
Initial values, memories, and Yosys Support	11	2557	April 16, 2021
How to avoid derived clock domains (i.e. ripple counter) FAQ	6	573	March 16, 2021
How to infer to unique case Support	1	455	March 12, 2021
Design functions when the clock is inverted Support	2	464	February 18, 2021
Using lists of signals in myhdl Support	2	538	February 10, 2021
Type mismatch with earlier assignment: FAQ	15	627	February 5, 2021
AssertionError: Unexpected callable Support	8	700	January 6, 2021
Myhdl signed assignment fails at runtime Support	4	502	December 23, 2020
Use VHDL library Support	3	774	July 5, 2020
List of signals as a port is not supported : mem Support	1	768	March 26, 2020