Support

Bug The category is applied to support questions that could be bugs (and not limitations). Tests should be created for all topics with the Bug category and a pull-request generated. FAQ This category addresses frequently asked questions [FAQ], see also the myhdl.org FAQ page

Topic	Replies	Views	Activity
About the Support category Support	0	1013	May 15, 2016
Conditional conversion tricks? Support	3	86	July 14, 2025
Converting enum code (integer) to EnumItem Support	9	117	April 15, 2025
New to MyHDL - how should I connect outputs to inputs properly? Support	3	82	January 24, 2025
Cosimulation output port conflict (X) Support	2	58	October 4, 2024
Cosimulation with waveform dump Support	2	1128	October 1, 2024
Managing scattered codebase Support	0	33	September 30, 2024
VHDL constant value overflow Bug	16	3914	July 24, 2024
How to get the latest Version of myhdl 2 Support	4	558	February 26, 2023
How to get latest version of myhdl? Support	12	607	December 11, 2022
Pull Request Cleanup Support	1	365	December 8, 2022
myhdl.AlwaysCombError: sensitivity list is empty Support	1	519	November 9, 2022
Sub module Verilog synthesis error Support	3	569	June 17, 2022
Sign extend bits Support	2	709	May 10, 2022
Multiple @always_comb needed - why? Support	35	948	April 26, 2022
Signed error with lshift Support	3	468	April 24, 2022
Sanity check: Ps/2 Keyboard on an fpga Support	2	586	April 21, 2022
Preserve hierarchy Support	8	1234	April 19, 2022
I am implementing single cycle processor, RV32I ... i am facing issues in top module.. file named as " core.py " Support	1	579	December 9, 2021
I am having issue, when i am converting myhdl to verilog it gives me error on list indexing Bug	0	488	November 29, 2021
Is MyHDL a good choice to create BFMs? FAQ	6	810	November 16, 2021
Shadow Signals are not updating Support	2	540	September 20, 2021
Natural method for expressing horizontal microcode? Support	4	573	August 23, 2021
Modelling wired-or (wired-and) bus behaviour Support	4	585	August 23, 2021
Result of multiplication is zero. Not so in simulation FAQ	9	704	June 13, 2021
Myhdl: how to set pin to 'high impedance' FAQ	1	600	May 17, 2021
Initial values, memories, and Yosys Support	11	2850	April 16, 2021
How to avoid derived clock domains (i.e. ripple counter) FAQ	6	650	March 16, 2021
How to infer to unique case Support	1	485	March 12, 2021
Design functions when the clock is inverted Support	2	501	February 18, 2021