Sign extend bits

Hi All,

I have a 4 bit number that I need to sign extend to say ‘WIDTH’ bits … I have read online some older banter but not sure out of that how to do this or if it is supported easily?

I can of course use an if then to test the bit and stuff ones/zeroes …the verilog version is simple (I suspect VHDL is similarly so)

rt <= {{WIDTH-4{instr[3]}}, instr[3:0]}; // using bit replication



let’s take WIDTH == 8 (for simplicity)
let’s assume that you declared rt = Signal(intbv(0,-128,128))

  • then either you have declared instr = Signal(intbv(0,-8,8)) and = instr is automatically sign-extended
  • or you have declared instr = Signal(intbv(0)[4:]) you can say = instr.signed() and the sign extension is again automatic.

but if you have declared rt = Signal(intbv(0)[8:]) things get ugly: = concat(instr[3], instr[3], instr[3], instr[3], instr)

VHDL: rt <= resize(instr, WIDTH);


Thanks Josy,

I fell into the last condition, so I declared rt as Signed(intbv(0, -2**(WIDTH-1), 2**(WIDTH-1))) which made my rt as reg signed which is a great outcome and so used instr.signed() - thanks!