VHDL conversion bug (resize of signed signal)?

Support Bug
1

Before submitting a bug I’d like to check my assumptions are correct.

I have the following in a design :

def AudioSample(reset_value=0, nb_bits=24):
    return intbv(0, min=-(2**(nb_bits-1)), max=2**(nb_bits-1))      # min included ; max excluded

@block
def my_code():
    ...
    Add    = Signal(AudioSample(0, 2+len(Mul0)))
    Result    = Signal(AudioSample(0, 1+len(Add)-self.norm_size))
    RoundingValue = AudioSample(0, len(Result))
    ...
    @always_seq(i_Clk.posedge, reset=None)
    def compute_proc() :
        ....
        Result.next = Add[:norm_size] + RoundingValue
        ...
    ...

Part of the generated code is the following :

... 
signal Add: signed (49 downto 0) := 50X"0000000000000";
signal Result: signed (30 downto 0) := 31X"00000000";
...

COMPUTE_PROC: process (i_Clk) is
    variable RoundingValue: signed(30 downto 0);
begin
...
        Result <= (signed(resize(unsigned(Add(50-1 downto 20)), 31)) + RoundingValue);
....

The problem is in the resizing of Add signal.
I think that Add shall not be casted to unsigned before resizing. By casting Add to unsigned, the sign bit is lost during the resize.
Am I right ?

2

Nicolas,

I think it is a bug. All of my work is with unsigned values (cameras) so I haven’t run into this often and if, I have probably a local work-around. E.g. I have expanded the ShadowSignal() to accept a SIGNED= parameter.

Regards,

Josy

3

Josy,

What I don’t understand is that the cast is explicitly done in conversion code (_toVHDL.py lines 1496-1498) :

        if isinstance(node.value.vhd, vhd_signed) and isinstance(node.ctx, ast.Load):
            pre = pre + "unsigned("
            suf = ")" + suf

Does this solve problems with specific situations ?
I am reluctant at modifying MyHDL source code since my understanding is limited.

Regards,
Nicolas

4

Nicolas,

It is not clear to me, either. And this node.value.vhd stuff is tricky, indeed.
But I’m almost sure you can comment-out that piece.

Regards,
JOsy

5

Josy,

That’s what I did. I then rerun the conversion of existing projects (which don’t use signed signals) and compared to preceding conversion result (that’s why I added the sort of signals and process sensitivity list). I didn’t notice any difference in the conversion result.

Regards,
Nicolas