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Welcome to the MyHDL Discussion forum!
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0
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2492
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May 15, 2016
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Sign extend bits
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2
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29
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May 10, 2022
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Multiple @always_comb needed - why?
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35
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51
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April 26, 2022
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Signed error with lshift
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3
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28
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April 24, 2022
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ToVerilogWarning: Output port is read internally:
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6
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35
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April 23, 2022
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Sanity check: Ps/2 Keyboard on an fpga
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2
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54
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April 21, 2022
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Preserve hierarchy
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8
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556
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April 19, 2022
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MyHDL synthesis support / jupyosys
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1
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457
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January 26, 2022
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Trying to create a fifo through a queue
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7
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94
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January 20, 2022
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How to do cosimulation with a commercial tool?
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3
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84
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January 11, 2022
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Creating a group of Signals
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5
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91
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January 4, 2022
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MyHDL Signals inside functions not showing up in VCD
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1
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65
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January 2, 2022
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Initial block in MyHDL
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2
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78
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January 1, 2022
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Long integer translation
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5
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76
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December 15, 2021
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I am implementing single cycle processor, RV32I ... i am facing issues in top module.. file named as " core.py "
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1
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102
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December 9, 2021
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I am having issue, when i am converting myhdl to verilog it gives me error on list indexing
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0
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81
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November 29, 2021
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Is MyHDL a good choice to create BFMs?
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6
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187
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November 16, 2021
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Type mismatch with earlier assignment
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3
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97
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October 28, 2021
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Variables in VHDL
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3
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157
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October 17, 2021
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Shadow Signals are not updating
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2
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137
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September 20, 2021
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First attempt with MyHDL
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1
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172
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September 16, 2021
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Natural method for expressing horizontal microcode?
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4
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176
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August 23, 2021
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Modelling wired-or (wired-and) bus behaviour
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4
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176
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August 23, 2021
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A future for the MyHDL community?
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76
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5873
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June 26, 2021
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Result of multiplication is zero. Not so in simulation
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9
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221
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June 13, 2021
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Myhdl: how to set pin to 'high impedance'
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1
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192
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May 17, 2021
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Initial values, memories, and Yosys
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11
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1265
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April 16, 2021
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Setup MyHDL to evaluate
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3
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204
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April 9, 2021
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How to avoid derived clock domains (i.e. ripple counter)
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6
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210
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March 16, 2021
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How to infer to unique case
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1
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179
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March 12, 2021
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