Hi All,
I want to shift a signal left if the msbit is false in a clocked process… (Verilog has no issue with this)
shift.next = mult << ~mult[WIDTH2M-1]
i.e. of mult[WIDTH2M-1] is false, shift left otherwise do not.
This gives an error
File “D:\Lumetrica_Projects\myHDL_IP\math\floating_point\fp_multiply.py”, line 41, in comb2_logic
shift.next = mult << int(~mult[WIDTH2M-1])
File “d:\lumetrica_projects\adc_interface\src\myhdl\myhdl_Signal.py”, line 434, in lshift
return self._val << other
File “d:\lumetrica_projects\adc_interface\src\myhdl\myhdl_intbv.py”, line 257, in lshift
return intbv(int(self._val) << other)
ValueError: negative shift count
My Signals are modbv() and not intbv - if that matters
If there is a way to cast this to avoid the error I haven’t found it yet.
Turning it into an ‘if … else’ is really quite messy.- but I guess I can do this.
Do I register this as a bug or is it correct behaviour?
Regards,
Steve.