Preserve hierarchy

Support
1

Hello,

I see that for all the myhdl sub modules that during conversion, the hierarchy is flattened.
Is there an easy solution to preserve hierarchies ?
Is this feature available now ?

Thank you

2

Hi,
The way MyHDL currently works flattens the hierarchy. There is no option to keep it in the converted design.
However, this is in the todo list.

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3

The preserve hierarchy is only partially supported, you will have to manually pull the different sub-blocks together.

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4

Hello felton,

Thank you very much for the reply.
Is it by using some conditional instantiation ?
Is there any documentation for it to do the best way?

Thanks

5

No there is not any documentation currently, in the old mailing-list (is gmane back online yet?) there are some conversations that elude to the procedure.

I personally have not experimented with preserving hierarchy, although I was part of the conversations way back when. I will poke around and see if I can find some of the old conversations and/or put together a simple example.

Regards,
Chris

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6

Hello Chris,

Did you find the example about preserving hierarchy while conversion?
It would be great if you could provide some info on it.

Regards
Sheshu

7

Sorry to necropost, but this topic is exactly what I am looking for. I want to be able to instantiate BFM models that can mimic xilinx IP in simulation, like a cordic or block ram memories.

I can create something that works in simulations, but for synthesis I would like to be able to drop it out and replace with the IP, I don’t see how this is possible if everything gets flattened.

8

Dave,

It is fine to resurrect things (now and then) …
More people, me included) are interested in getting an hierarchic conversion, but I never found the time to devote to this rather large project.
There is an implementation for the pre- 0.10 MyHDL version by Jose M. Gomez (GitHub - jmgc/myhdl-numeric: Myhdl fork that includes support for multiple entities (MEP110) and fixed point functionality (MEP 111) on VHDL. See myhdl/numeric dir under the numeric branch, and the Cordic example (example/cordic/Cordic.ipynb).). Maybe we can convince him to port the hierarchy code to 0.11? I sent him an e-mail.

Reagrds,
Josy

9

@davekeeshan There’s a hack that allows you to switch IP using __vhdl__ or __verilog__ variables, kind of allowing @blackbox style instancing, e.g.:

def stackmem_wrapper_ipx(clk, pa_wdata, pa_rdata, pa_we, pa_addr, \
                          pb_wdata, pb_rdata, pb_we, pb_addr):

	@always(clk.posedge)
	def dummy():
		pass

	__vhdl__ = \
"""
stackmem_distram: entity work.machxo2_stackmem
	port map (
        WrAddress   => std_logic_vector(%(pa_addr)s),
        Data        => std_logic_vector(%(pa_wdata)s),
        WrClock     => clk,
        WE          => %(pa_we)s,
        WrClockEn   => '1',
        RdAddress   => std_logic_vector(%(pb_addr)s),
        Q           => %(pb_rdata)s
	);
"""

	return dummy

Not a really viable solution though for wrapping larger libraries, I’m afraid.
Even though there are a few myhdl forks that implemented hierarchy awareness and blackboxes, there are plenty of issues to be dealt with that are hard to handle with the current MyHDL ‘kernel’.

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