Convert FROM vhdl

Hi everyone,

I am very new here, an I would like to ask a couple a question:
I am currently working on a project done in VHDL, and I want to port it to the open source toolchain made for Lattice FPGA.
for what I know, that toolchain works only with verilog, so I will have to translate from vhdl to verilog.
But, since I have to make a translation I can make it to myHDL.

Is it a good idea? is there any library that does this translation automatically?

Thanks in advance for any answer

  1. Ask the open source toolchain folks to implement the VHDL front-end!
  2. Rewrite your VHDL code into MyHDL and have it generate Verilog (and VHDL to check/compare)

The options are not directly mutually exclusive :smile: