I’m finding my way around MyHDL. I’m well-versed in VHDL and experienced with Python, but as another post mentioned recently, there’s an open-source toolchain for Lattice FPGAs but it only supports Verilog, so I’m looking at using MyHDL for my authoritative code base and then converting to Verilog for synthesis, and VHDL for sanity-checking and maybe extra debugging. The ability to write Python unit tests with MyHDL is the major drawcard for me.
I’ve read through most (but not all) of the MyHDL docs in the main documentation area, and I feel like I understand most of what is going on, but I’m still learning the ropes. In particular, the code below successfully generates VHDL, but there’s no definition of the signal
pattern generated, so I don’t think this will synthesise.
from myhdl import block, always, always_comb, Signal, intbv, modbv PATTERN_SOS = intbv("101010001110111011100010101") @block def Blink(clk, clk_en, led): pattern = PATTERN_SOS counter = Signal(modbv(0, min=0, max=32)) @always(clk.posedge) def counter_inc(): if clk_en == 1: counter.next = counter + 1 @always_comb def output(): led.next = pattern[counter] return counter_inc, output if __name__ == "__main__": inst = Blink(Signal(bool(0)), Signal(bool(0)), Signal(bool(0))) inst.convert(hdl="VHDL")
-- File: Blink.vhd -- Generated by MyHDL 0.10 -- Date: Sun Jul 29 17:59:49 2018 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use std.textio.all; use work.pck_myhdl_010.all; entity Blink is port ( clk: in std_logic; clk_en: in std_logic; led: out std_logic ); end entity Blink; architecture MyHDL of Blink is signal counter: unsigned(4 downto 0); begin BLINK_COUNTER_INC: process (clk) is begin if rising_edge(clk) then if (clk_en = '1') then counter <= (counter + 1); end if; end if; end process BLINK_COUNTER_INC; led <= pattern(to_integer(counter)); end architecture MyHDL;
Is there some special treatment I need to make to
PATTERN_SOS to have it convert successfully? Is it possible to declare it a constant array or somesuch?
Incidentally, this simple change (using
PATTERN_SOS directly rather than via an alias) doesn’t convert:
@block def Blink(clk, clk_en, led): counter = Signal(modbv(0, min=0, max=32)) @always(clk.posedge) def counter_inc(): if clk_en == 1: counter.next = counter + 1 @always_comb def output(): led.next = PATTERN_SOS[counter] return counter_inc, output
Traceback (most recent call last): File "blink.py", line 58, in <module> inst.convert(hdl="VHDL") ... myhdl.ConversionError: in file blink.py, line 51: Object type is not supported in this context: PATTERN_SOS, <class 'myhdl._intbv.intbv'>
In Python there should be absolutely no difference in behaviour between an alias and the aliased object, but in this case there seems to be a distinction made. Can anyone shed light on this please? It’s unexpected to me.