Problem while converting to VHDL code

Support
1

  1. While verifying converted output into verilog and vhdl sequentially as in below, it causes problems.

    def test_convertible():

     @block
 def test():
     hostmanagement_interface = HostManagementInterface()
     mdio_interface = MDIOInterface()
     reset = ResetSignal(1, active=0, async=True)
     dutInst = management(hostmanagement_interface, mdio_interface, reset)
     print("Testing Convertibility %s" % dutInst)

     @instance
     def hostclkdriver():
         while True:
             hostmanagement_interface.clk.next = \
                 not hostmanagement_interface.clk
             yield delay(5)

     @instance
     def testlogic():
         yield delay(20)
         print("Converted!")
         raise StopSimulation

     return dutInst, testlogic, hostclkdriver

 testInst = test()
 verify.simulator = 'iverilog'
 assert testInst.verify_convert() == 0
 verify.simulator = 'ghdl'
 assert testInst.verify_convert() == 0

Error:



E               AttributeError: ‘NoneType’ object has no attribute ‘f_globals’

File “C:\Users\Ravi\virtualenvs\myhdl_WinCosim\lib\site-packages\myhdl-1.0.dev0-py3.5.egg\myhdl\conversion_analyze.py”, line 174
AttributeError

2 .

MyHDL Snippet.

mdiodata.rddata.next = mdiodata.rddata |  (mdio_interface.inn << mdiodata.rdindex)

Converted to:

management_6_mdiodata_rddata <= (management_6_mdiodata_rddata or to_unsigned(shift_left(management_6_mdio_interface_inn, to_integer(management_6_mdiodata_rdindex)), 16));

Error:

test.vhd:259:112: no overloaded function found matching 'shift_left'

test.vhd:259:101: no overloaded function found matching 'to_unsigned'

By spltting the above assignment use to to_unsigned can be avoided but problem persists with shift_left.

2

@Ravi_Jain when posting issues / problems you should sandbox the problem, make sure you can repeat it with a simple example. After you have done the sandbox experiment, then post the code for the simple example. This helps: 1) it shows you have done due diligence trying to resolve the issue; 2) others can easily exercise the code snip in question and provide feedback.

Regards,
Chris

3

@Ravi_Jain also, since you are not doing cosimulation you should use the master branch and not the @josyb branch (for now). It will be easier to debug if there is a problem.

4

@Ravi_Jain you need to deal with the first error, switch back to the myhdl master branch.

5

I shall keep that(@sandboxing a problem) in mind from the next time I post.
The simple example : https://gist.github.com/ravijain056/8e9bff5d7a16b95cb24a7d777711bbb1

I am using the master branch from the beginning.

The first error persists in the example.
I found the a workaround for second error while trying to sandbox the problem. The problem being usage of boolean as a signal.(As per my understanding).
Getting new error after solving the second.

ghdl.exe: Cannot find entity or configuration test_top.

Side problem faced : variable name out clashes with reserved keyword in vhdl.

Ghdl version used - 0.33 - win32 : https://sourceforge.net/projects/ghdl-updates/files/Builds/ghdl-0.33/

6

@josyb
Hey could you check up on the ghdl setup for windows i am using. Not so confident.

Ghdl version used - 0.33 - win32 : https://sourceforge.net/projects/ghdl-updates/files/Builds/ghdl-0.33/

7

I too have a problem with GHDL, so I use the Altera Starter Edition version of ModelSIm :grinning:

8

@Ravi_Jain with your sandbox version I get no errors, tested with vcom and iverilog, I don’t have the latest version of GHDL installed.

9

@Ravi_Jain feel free to only test verilog and move on at this point.

10

Did you uncomment verify_convert() lines at the bottom? To test the first error.

11

Yes, I indicated I tested modelsim VHDL and Icarus verilog:

verify.simulator = 'iverilog'
assert testInst.verify_convert() == 0

verify.simulator = 'vcom'
assert testInst.verify_convert() == 0

I tested in two separate runs, not executed back to back.

12

The problem is that the error comes up when you try to do it in one run.

13

Don’t do that then.

(it says I need 20 chars)
(…)

14

Okay, I will just use verilog and move on then.

15

Re-instantiate it before testing the conversion again.

testInst = test_top()
verify.simulator = 'iverilog'
assert testInst.verify_convert() == 0

testInst = test_top()
verify.simulator = 'vcom'
assert testInst.verify_convert() == 0