that’s two issues in one
I can’t help much on the first (Verilog is not my thing …)
The second:
You don’t need to append the [32:] slicing operation if the width of the concat result is equal to 32.
This little snippet demonstrates two problems, first the literal generation for the reset assignment that @Ravi_Jain stumbled upon. Second, the odd signal state issue @hgomersall describes in #176. The second is more of an annoyance with the incorrect
warning message.
// File: myblock.v
// Generated by MyHDL 1.0dev
// Date: Thu Jun 16 07:48:50 2016
`timescale 1ns/10ps
module myblock (
clock,
reset,
inc,
out
);
input clock;
input reset;
input inc;
output [31:0] out;
reg [31:0] out;
reg [4:0] rdindex;
reg [5:0] wrindex;
always @(posedge clock) begin: MYBLOCK_BEH
if (reset == 1) begin
wrindex <= 3e;
out <= 00000000;
rdindex <= 11;
end
else begin
out <= (rdindex + wrindex);
if (inc) begin
rdindex <= (rdindex + 1);
wrindex <= (wrindex + 1);
end
end
end
endmodule
Converted VHDL
-- File: myblock.vhd
-- Generated by MyHDL 1.0dev
-- Date: Thu Jun 16 07:49:34 2016
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_10.all;
entity myblock is
port (
clock: in std_logic;
reset: in std_logic;
inc: in std_logic;
out: out unsigned(31 downto 0)
);
end entity myblock;
architecture MyHDL of myblock is
signal rdindex: unsigned(4 downto 0);
signal wrindex: unsigned(5 downto 0);
begin
MYBLOCK_BEH: process (clock) is
begin
if rising_edge(clock) then
if (reset = '1') then
wrindex <= to_unsigned(3e, 6);
out <= to_unsigned(00000000, 32);
rdindex <= to_unsigned(11, 5);
else
out <= (resize(rdindex, 32) + wrindex);
if bool(inc) then
rdindex <= (rdindex + 1);
wrindex <= (wrindex + 1);
end if;
end if;
end if;
end process MYBLOCK_BEH;
end architecture MyHDL;
@Ravi_Jain can you create a test for this and create a PR to the myhdl repository. See @sriramesh4test as an example.
It did work OK some commits ago …
If I run @cfelton’s through my local MyHDL library I get correct behaviour:
Verilog:
always @(posedge clock) begin: myblock_beh
if (reset == 1) begin
outp <= 0;
rdindex <= 17;
wrindex <= 62;
end
VHDL:
beh : process(clock) is
begin
if rising_edge(clock) then
if (reset = '1') then
outp <= to_unsigned(0, 32);
rdindex <= to_unsigned(17, 5);
wrindex <= to_unsigned(62, 6);
else
I think (not sure) it was broke when some minor changes were made to support IVS, specifically the larger than 32bit initial values.
I think this is the change that broke it. It was the unforeseen downstream that didn’t create the correct literal format.
This is a perfect task for @Ravi_Jain, to create a myhdl test in the bugs and expand the always_seq conversion tests in test/conversion/general (actually, since this is still 1.0dev I guess we don’t create a bug test but rather increase the test suite coverage).
The fix would be to make sure the init representation is a hex string always and then modify the V* writes to format correctly.
@ 2nd problem
Still if i want to slice it in an unorthodox way like, [30:16], etc. The Conversion should take care of it, right? Throw up some error or Warning at least.
Looks like your workaround, using an intermediate signal, is the best option. I can think of a way to do this in VHDL, but don’t know Verilog well enough to even have an idea.
