I am having issue, when i am converting myhdl to verilog it gives me error on list indexing

Support questions that have been identified as possible bugs. A test case needs to be created for each of these and a merge request created to the myhdl repository.

here is the code

from myhdl import *

import array as arr

rows = 32

DW = 2**(rows-1)

RegArray = [Signal(intbv(0,-DW,DW)) for i in range(rows+1)]


def RegFile(rs_A,rs_B,Rd,WriteBack , WriteEnable, Data_A, Data_B):


def read(): = RegArray[int(rs_A)] = RegArray[int(rs_B)]


def write():

    if WriteEnable == 1 and int(Rd) != 0 :

        RegArray[Rd].next =  WriteBack

return read, write


def SimulateReg():

rs_A = Signal(intbv(1,0,rows+1))

rs_B = Signal(intbv(13,0,rows+1))

Rd = Signal(intbv(1,0,rows+1))

WriteBack = Signal(intbv(200,-DW,DW))

writeEnable = Signal(intbv(1,0,2))

Data_A = Signal(intbv(0,-DW,DW))

Data_B = Signal(intbv(0,-DW,DW))

regg = RegFile(rs_A,rs_B,Rd,WriteBack,writeEnable,Data_A,Data_B)

# regg.convert('Verilog')


def simulatingReg():

    for i in range(1):

        yield delay(10)

        print("rs_a : ",int(rs_A))

        print("rs_b : ",int(rs_B))

        print("rd : ",int(Rd))

        print("writeback : ",int(WriteBack))

        print("writeEnable : ",int(writeEnable))

        print("data A : ",int(Data_A))

        print("data B : ",int(Data_B))


return regg, simulatingReg

tb = SimulateReg()