Moving to 0.1dev broke my design

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1

I updated my version of MyHDL and my code broke. It looks like conversion to .v worked but the test/simulation failed. After spending hours on the forums, I have not recovered that part yet.

This is what worked end-to-end in v0.9.

from myhdl import *


CLOCK = 40
HALF_CLOCK = delay(int(CLOCK / 2))
WIDTH = 32


def counter(clock, reset, clear, enable, count):

    @always(clock.posedge, reset.posedge)
    def logic():

        if reset or clear:
            count.next = 0
        elif enable:
            count.next = count + 1

    return logic


def test():

    clock = Signal(bool(0))
    reset = Signal(bool(0))
    clear = Signal(bool(0))
    enable = Signal(bool(0))
    count = Signal(intbv(0)[WIDTH:0])

    inst = counter(clock, reset, clear, enable, count)

    @always(HALF_CLOCK)
    def clock_generator():
        clock.next = not clock

    @instance
    def reset_generator():
        reset.next = True
        yield delay(100)
        reset.next = False
        while True:
            yield delay(1000)

    @instance
    def stimulus():
        yield delay(150)
        enable.next = True
        yield delay(1000)
        enable.next = False

        yield delay(100)
        clear.next = True
        yield delay(CLOCK)
        clear.next = False

    return inst, clock_generator, reset_generator, stimulus


def simulate(n):
    tb = traceSignals(test)
    sim = Simulation(tb)
    sim.run(n)


def convert():
    clock = Signal(bool(0))
    reset = Signal(bool(0))
    clear = Signal(bool(0))
    enable = Signal(bool(0))
    count = Signal(intbv(0)[WIDTH:0])

    toVerilog(counter, clock, reset, clear, enable, count)


if __name__ == '__main__':
    convert()
    simulate(20000)

When I run this in 0.1dev, I get this and no .vcd file is generated.

C:/MyPython/myhdl_demo/counter.py:72: UserWarning: 
	toVerilog(): Deprecated usage: See http://dev.myhdl.org/meps/mep-114.html
  toVerilog(counter, clock, reset, clear, enable, count)
C:\MyPython\myhdl_demo\venv\lib\site-packages\myhdl\conversion\_toVerilog.py:296: ToVerilogWarning: Output port is read internally: count
  category=ToVerilogWarning
C:/MyPython/myhdl_demo/counter.py:60: UserWarning: 
	traceSignals(): Deprecated usage: See http://dev.myhdl.org/meps/mep-114.html
  tb = traceSignals(test)
<class 'myhdl._SuspendSimulation'>: Simulated 20000 timesteps

Process finished with exit code 0

It must be something simple but I haven’t found it yet.

Thanks.

2

Nothing broke …
I ran your code locally and it generates the Verilog code and the .vcd file:

image
image.png843×503 25.2 KB

In MyHDL 0,1dev a new decorator @block has been introduced and the warnings printed out have to do with the fact that you haven’t used it. Unfortunately they are sent to stderr and hence turn up red.

It is the idea that in the next release this @block decorator usage will become mandatory as it opens up possibilities to enhance the V* code generation among others.

Maybe someone (@cfelton, @devbisme, …) can find the time to make a short but all-inclusive example?

Regards,
Josy

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