MyHDL

Function not converting, but deflated code does

Dear All,
Well I try something that is simplistic, but I have a low mileage on Myhdl. If one of the senior here around could have a look and explain the beginner where he is mistaken he would be very thankful :slight_smile:
First code simulate but doesn’t convert:

def Stream(sig_01, period, idx, buffer, txdata):
    sig_01.next = 0  

    yield delay(period)
    
    while(idx < len(buffer)):
        txdata.next = buffer[int(idx)]
        idx.next =  idx + 1 
        yield delay(period)
        
    idx.next = 0
    sig_01.next = 1 
    yield delay(2*period)

@block
def Top_verif_01(RSTn, ENBn, TXD):    
    ''' Top signals '''
    rstn = ResetSignal(1, active=0, isasync = True)
    enbn = Signal(bool(1))    
    txd = Signal(bool(0))

    ''' internal signals '''
    depth = 256      
    txdata =Signal(intbv(0)[8:])
    idx =  Signal(intbv(0, 0, depth ))
    sys_clk = Signal(bool(0))
    frequency = 24e6 # Frequency 24MHz
    period = int(1./frequency * 1e9) # put the period in nano second
    half_period = int(period/2)  
    
    buffer = ( 0x83, 0x55, 0xA1, 0xFF, 0xF1 )
    buffer1 = ( 0x71, 0x88 )
                   
    @instance
    def signal_clk():
        while True:
            sys_clk.next = not sys_clk
            yield delay(half_period)
            
    @always_comb
    def slice_shadower():
        RSTn.next = rstn
        ENBn.next = enbn
        TXD.next = txd  

    @instance  
    def tx_signal():
        rstn.next = 1
        enbn.next = 1 
        yield delay(2 * period)
        rstn.next = 0
        yield delay(4 * period)
        rstn.next = 1
        
        yield delay(2 * period)
        
        yield(Stream(enbn, period, idx, buffer, txdata))
        print('1st Stream')
        yield(Stream(enbn, period, idx, buffer1, txdata))
        print('2snd Stream')

        raise StopSimulation 
                                   
    return instances()

Second code removing the def stream() and replacing the code inside the block does simulate and convert. Why ? For a good reason that I am missing yet.

        #yield(Stream(enbn, period, idx, buffer, txdata))
        enbn.next = 0  
    
        yield delay(period)
        
        while(idx < len(buffer)):
            txdata.next = buffer[int(idx)]
            idx.next =  idx + 1 
            yield delay(period)
            
        idx.next = 0
        enbn.next = 1 
        yield delay(2*period)  
              
        print('1st Stream')
        enbn.next = 0  
    
        yield delay(period)
        
        while(idx < len(buffer1)):
            txdata.next = buffer1[int(idx)]
            idx.next =  idx + 1 
            yield delay(period)
            
        idx.next = 0
        enbn.next = 1 
        yield delay(2*period)        
        #yield(Stream(enbn, period, idx, buffer1, txdata))
        print('2snd Stream')

Test results and converts

--------------------------------------------------------------------------------------------
test_top (__main__.Test) ... 1st Stream
2snd Stream
ok
test_top_convert (__main__.Test) ... C:\Py36-32_VirtEnv\VirtEnv_02\lib\site-packages\myhdl\conversion\_toVerilog.py:327: ToVerilogWarning: Signal is driven but not read: txdata
  category=ToVerilogWarning
C:\Py36-32_VirtEnv\VirtEnv_02\lib\site-packages\myhdl\conversion\_toVerilog.py:349: ToVerilogWarning: Signal is not driven: txd
  category=ToVerilogWarning
ok

----------------------------------------------------------------------
Ran 2 tests in 0.094s

OK

Hi,

Can you please edit your code and format it correctly to make it easily readable ?
Please see here : https://github.com/adam-p/markdown-here/wiki/Markdown-Cheatsheet#code

Bonjour DrPi,
OK c’est fait.

Beaucoup mieux :wink:

I’ll look at it when I have time.

Can you please provide the code you use for conversion ?

Here it is. Le voila :grin:

    def test_top_01(self):      
        tb = tb_Top_verif_01()
        #traceSignals.timescale = '1ns'
        tb.config_sim(trace=True, directory = vcd_path)
        tb.run_sim()

    def test_top_tb_convert(self):   
        ENBn = Signal(bool(1))
        RSTn = ResetSignal(1, active=0, isasync=True)
        TXD = Signal(bool(0)) 
                          
        Top_verif_01_v =  Top_verif_01(RSTn, ENBn, TXD)
        Top_verif_01_v.convert(hdl='Verilog', directory = verilog_path, no_myhdl_header = True, header = custom_header, initial_values=True)

What’s the problem? Is it the warning? It looks like it is converting to me.

@hgomersall The provided code doesn’t convert.
The conversion stops with an error : Not supported: call to a generator function

@Dani I briefly chat with devs this morning. As the message error says, this is not supported (except for delays). Looks like the support of such a functionality could be added in the future but this would require much work.

@Henry,

Dear Henry,

If I use the function calls the code simulates, but is not converted in verilog.

If I simply copy past the function inside the @block it simulates and convert ( I don’t mind the warnings at this stage they can be managed).

It looks very simple code. Have a nice week end. Dani