MyHDL

First attempt with MyHDL

In a first attempt to use MyHDL I converted some VHDL lines to MyHDL. I tried to do this as good as possible. Because I want to use MyHDL for building reference models and use them in a VHDL testbench, I tried to convert the Python lines to VHDL. I got some error message which I can not get solved. I probably made some stupid (beginners) errors. Can someone tell me what is wrong with my code?

emphasized text
from myhdl import block, instance, always_seq, toVHDL, Signal

@block
def cropper(ip_rst, ip_clk, I2F_image_to_cropper, I2F_image_from_cropper, I2F_wait_to_cropper, I2F_wait_from_cropper, Cropperprm, ResetError):

To avoid the header fifo being read before the first header word has rippled through

an extra register delay is added in the cropper processing pipe (Header fifo ripple requires 3 clocks)

@instance
def register_buffer(ip_clk, ResetError, dHold, Input):

BufferOutput_Format = intbv(0, min=0, max=16) # from min to max-1

BufferOutput_Data = intbv(0, min=0, max=65536) # from min to max-1

BufferOutput_Defect = intbv(0, min=0, max=2) # from min to max-1

@always_seq(ip_clk.posedge)
def RegisterBuffer():
  if ResetError == 1:
    BufferOutput.Format = c_IDLE
    BufferOutput.Data   = 0
    BufferOutput.Defect = 0
  elif dHold == 0:
    BufferOutput.Format = Input.Format
    BufferOutput.Data   = Input.Data
    BufferOutput.Defect = Input.Defect
    
return RegisterBuffer    

@instance
def Wait_to_prev(ip_clk, ip_rst):

if ip_rst == 1:
  dHold = 0

@always_seq(ip_clk.posedge)
def wait():
  dHold = WaitIn

return dHold    

def convert_cropper(hdl):
#assign default/initial values to signals

ip_rst = Signal(bool(1)) # 1 = default/initial value
ip_clk = Signal(bool(0))
BufferOutput = Signal(int(0))
I2F_image_to_cropper = Signal(int(0))
I2F_image_from_cropper = Signal(int(0))
I2F_wait_to_cropper = Signal(bool(0))
I2F_wait_from_cropper = Signal(bool(0))
Cropperprm = Signal(int(0))
ResetError = Signal(bool(0))

inc_1 = cropper(ip_rst, ip_clk, I2F_image_to_cropper, I2F_image_from_cropper, I2F_wait_to_cropper, I2F_wait_from_cropper, Cropperprm, ResetError)
inc_1.convert(hdl)

convert_cropper(hdl=‘VHDL’)

After a lot of changes I managed to convert my first MyHDL code to VHDL. My code contained a lot of errors. Still a lot to learn!