From myHDL to syntesis

Hi everyone,
I am very new in the FGPA world, and I am making the first steps.
I have a little myHDL program and I am trying to synthesize it. (converting to Verilog, then using icestorm)
the simulation works as intended, and I want to move it in the FPGA.
I added the input output pin in the verilog, any way to do it in myhdl?
now icestorm is giving me an error…
is there any procedure that I should follow? because now I am doing pretty random things…
Thansk to anyone who help me

You are advised to post the code. So we can give you ‘directed’ help.

here, I have made a repo with the files. and are the files in myHDL
test_random.v is the verilog generated file
and in test_random_corrected.v i have made some changes that make it compile.
I feel that after my changes I should re-simulate.

then there is a makefile and example-8k.pcf that declares the connection between signals and pins.

I made a PullRequest with some small changes … you were close

Thanks!! obviously I have to give input and output to the block! Thank you very much!


I am sorry, but I have to ask for help again:
I made a couple of examples in my repo: blink and shift.
blink blinks but shift doesn’t shifts, yesterday I thought it was an issue with the pcf file, but the same pcf with blink works.
The myHDL code seems fine, and the simulation agrees, but the FPGA disagree… can you please give another look?

I got it! It was an initialization problem!
the translation to verilog forget to assign the initial value… should I write the myHDL code in a different way?

sorry, I should study before writing.
that’s it

Hehe - Interesting.

I’m a long-time myhdl user. I was waiting for initial_value support for quite some time.
I did not always follow the discussions but always read the “what’s new” sections in the manual.

However, this is the fist time that I found that initial value support is implemented.

Why isn’t this menioned in the manual?
Do I have to read the source code to find out what’s implemented?