Enhancement Request

MEP This category can be used to discuss myhdl enhancement proposals (MEP). These discussions can lead to the posting of a MEP. See the MEP guidelines for more information on the enhancement proposals process inspired by the python enhancement proposal (PEP) process.

Topic	Replies	Views	Activity
About the Enhancement Request category Enhancement Request	0	970	October 6, 2016
ToVerilogWarning: Output port is read internally: Enhancement Request	6	629	April 23, 2022
Cosimulation with verilator? Enhancement Request	13	1572	April 14, 2020
Allow kwargs in module interfaces Enhancement Request	3	940	January 21, 2020
Simplified signal naming when possible Enhancement Request	6	1071	January 20, 2020
Could modbv support non powers of two? Enhancement Request	10	1195	December 23, 2018
Coalesce identical sequential blocks into the same block? Enhancement Request	9	1015	December 22, 2018
Conversion hierarchy extraction? Enhancement Request	8	849	December 10, 2018
VHDL Bit string representation Enhancement Request	15	1998	November 5, 2018
Formal methods and MyHDL Enhancement Request	2	997	August 29, 2018
Add new Bool type to MyHDL? Enhancement Request	9	914	July 5, 2018
Matching a signal against a bitvector Enhancement Request	9	1395	July 1, 2018
Sort signal declarations in generated VHDL Enhancement Request	3	1017	October 5, 2017
Add support for nested functions Enhancement Request	4	1906	June 21, 2017
Making cosimulation more user friendly Enhancement Request	2	2068	April 26, 2017
On the design of state-machines Enhancement Request	3	1256	April 5, 2017
Generating hierarchical VHDL Enhancement Request	1	1095	March 2, 2017
Instanciate undefined Signal() Enhancement Request	8	1721	October 20, 2016
Intbv and the .next attribute Enhancement Request	2	1299	October 17, 2016
Conflict: print() Enhancement Request	5	1418	June 23, 2016