Enhancement Request

MEP This category can be used to discuss myhdl enhancement proposals (MEP). These discussions can lead to the posting of a MEP. See the MEP guidelines for more information on the enhancement proposals process inspired by the python enhancement proposal (PEP) process.

Topic	Replies	Views	Activity
About the Enhancement Request category Enhancement Request	0	996	October 6, 2016
ToVerilogWarning: Output port is read internally: Enhancement Request	6	952	April 23, 2022
Cosimulation with verilator? Enhancement Request	13	1957	April 14, 2020
Allow kwargs in module interfaces Enhancement Request	3	997	January 21, 2020
Simplified signal naming when possible Enhancement Request	6	1167	January 20, 2020
Could modbv support non powers of two? Enhancement Request	10	1418	December 23, 2018
Coalesce identical sequential blocks into the same block? Enhancement Request	9	1233	December 22, 2018
Conversion hierarchy extraction? Enhancement Request	8	1020	December 10, 2018
VHDL Bit string representation Enhancement Request	15	2384	November 5, 2018
Formal methods and MyHDL Enhancement Request	2	1050	August 29, 2018
Add new Bool type to MyHDL? Enhancement Request	9	1038	July 5, 2018
Matching a signal against a bitvector Enhancement Request	9	1595	July 1, 2018
Sort signal declarations in generated VHDL Enhancement Request	3	1113	October 5, 2017
Add support for nested functions Enhancement Request	4	2004	June 21, 2017
Making cosimulation more user friendly Enhancement Request	2	2151	April 26, 2017
On the design of state-machines Enhancement Request	3	1307	April 5, 2017
Generating hierarchical VHDL Enhancement Request	1	1142	March 2, 2017
Instanciate undefined Signal() Enhancement Request	8	1856	October 20, 2016
Intbv and the .next attribute Enhancement Request	2	1392	October 17, 2016
Conflict: print() Enhancement Request	5	1489	June 23, 2016