ToVerilogWarning: Output port is read internally:


I find I get benign warning for using my output of my block internally - this looks like a redundant message and should be removed? Its always nice to compile and not get any warnings / errors.



Hi Steve,

I suppose you mean this warning: “Output port is read internally”. This was valid for VHDL 1993, but for VHDL2008 we can remove this warning.
I believe the same holds for Verilog, it is a benign warning.
I assume you are converting to Verilog?

We will discuss this with others: @hgomersall


Is it actually benign? My understanding of the rationale is/was that output ports read internally could lead to timing issues. What’s changed for this to no longer be an issue?

VHDL 2008 allows reading of out ports. At some point MyHDL raised the VHDL version to 2008; so it is safe to remove the warning for VHDL conversion.
For Verilog it looks there is no issue either; perhaps in the early days of MyHDL (2003!) there might have been a restriction, and we never bothered to remove the warning.
We definitely have to rewrite the VHDL convertor to properly emit an out port instead of an inout port and remove the warning. For the Verilog convertor we just remove the warning, the out port is correctly instantiated.

Hi Josy,

Yes this is for Verilog (and hopefully one day SystemVerilog) - it seems benign as it is very legal to have a signal that feeds a GPIO and internal logic (especially safe when registered) - but I dislike warnings, as then i have to justify what they are. So then I have to create a copy signal that does the feedback etc. (well I think that is a work around)

I saw some chatter on this topic around 2016 but not sure if this is on the ‘to fix’ pile or if it fell off… it is a nice to have for sure, and not a bug.



Hi Steve,

I dislike warnings as much as you do - for me “A warning is an error waiting to happen” :slight_smile:
It is not on the ToDo-list AFAIK, but you are welcome to post this as an Issue.


Not sure about others, but I routinely read output ports in Verilog. I understand maybe there would be timing problems if it actually were to go outside a Pad and come back in. But my myHDL Verilog is not top level of the design, so it’s just an internal signal. Not supporting (or rejecting) the change request, just another data point. I just (script) ignore these myhdl warnings now.