ToVHDLWarning: Port is not used:

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1

While experimenting I got faced with this warning, and I can’t find out why …


from __future__ import print_function


from myhdl import Signal, intbv, always_seq, always_comb, block


@block
def fmux(Clk, Reset, Data, Selection, Result):
    @always_seq(Clk.posedge, reset=Reset)
    def reg():
        for i in range(len(Selection)):
            if Selection[i]:
                Result.next = Data[i]
    return reg


def convert():
    C_WIDTH_D = 8
    C_NUM_DATA = 6
    Clk = Signal(bool(0))
    Reset = None #ResetSignal(0, 1, True)
    Data = Signal(intbv(0)[C_NUM_DATA * C_WIDTH_D:])
    Selection = Signal(intbv(0)[C_NUM_DATA:])
    Result = Signal(intbv(0)[C_WIDTH_D:])

    @block
    def top3_mux(Clk, Reset, Data, Sel, Result):
        ldata = [ Signal(intbv(0)[C_WIDTH_D:]) for _ in  range(C_NUM_DATA)]
        @always_comb
        def assign():
            for i in  range(C_NUM_DATA):
                ldata[i].next = Data[(i+1)*C_WIDTH_D : i*C_WIDTH_D]
        mux3 =  fmux(Clk, Reset, ldata, Sel, Result)
        return mux3, assign


    print('converting top3_mux')
    top3_mux(Clk, Reset, Data, Selection, Result).convert('VHDL')

if __name__ == '__main__':
    convert()

I get this warning:
C:\Users\Josy\virtualenvs\london_app_dev\lib\site-packages\myhdl-1.0.dev0-py2.7.egg\myhdl\conversion\_toVHDL.py:369: ToVHDLWarning: Port is not used: Sel category=ToVHDLWarning

The converted VHDL is fine:

-- File: top3_mux.vhd
-- Generated by MyHDL 1.0dev
-- Date: Sun Jun  5 18:22:06 2016


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_10.all;

entity top3_mux is
	port(
		Clk    : in  std_logic;
		Data   : in  unsigned(47 downto 0);
		Sel    : in  unsigned(5 downto 0);
		Result : out unsigned(7 downto 0)
	);
end entity top3_mux;

architecture MyHDL of top3_mux is
	type t_array_ldata is array (0 to 6 - 1) of unsigned(7 downto 0);
	signal ldata : t_array_ldata;

begin
	TOP3_MUX_FMUX_0_REG : process(Clk) is
	begin
		if rising_edge(Clk) then
			for i in 0 to 6 - 1 loop
				if bool(Sel(i)) then
					Result <= ldata(i);
				end if;
			end loop;
		end if;
	end process TOP3_MUX_FMUX_0_REG;

	TOP3_MUX_ASSIGN : process(Data) is
	begin
		for i in 0 to 6 - 1 loop
			ldata(i) <= Data(((i + 1) * 8) - 1 downto (i * 8));
		end loop;
	end process TOP3_MUX_ASSIGN;

end architecture MyHDL;

So the warning should not have been issued.

2

I have a clue …
If I change the source to:

@block
def fmux(Clk, Reset, Data, Selection, Result):
    @always_seq(Clk.posedge, reset=Reset)
    def reg():
        if Selection != 0:
            for i in range(len(Selection)):
                if Selection[i]:
                    Result.next = Data[i]
    return reg

The warning stays away.
This means that for some strange reason the for i in range(...) hides Selection

3

It is not the for i in range(...). but the len() that causes the warning.
Changing the source code to:

@block
def fmux(Clk, Reset, Data, Selection, Result):
    NUM = len(Data)
    @always_seq(Clk.posedge, reset=Reset)
    def reg():
        for i in range(NUM):
            if Selection[i]:
                Result.next = Data[i]
    return reg

passes without warning.