Unlike VHDL, myhdl module signals are defined outside modules.
def module1(i_clk, o_data) : ... def module2(i_clk, i_data) : ... def module3() : i_clk = Signal(bool(0)) data = Signal(bool(0)) inst1 = module1(i_clk, data) inst2 = module2(i_clk, data) ...
In the above code, i_clk is declared/instantiated as a boolean in module3 and this is the right place to do this.
The problem is with data. It is also declared/instantiated in module3. The problem is that module3 should not have any knowledge of what module1 want this signal to be.
One consequence is that the default value is not controlled by module1 but by module3. This is not good behaviour.
Another consequence is that module3 must have some knowledge of module1 internals to declare the correct signal. This is not pythonic.
One solution could be to be able to declare a signal as undefined : my_signal = Signal()
The first time my_signal is assigned a value, it’s type is defined.
This allows to create “connector” signals between module without knowledge of their type. Like between module1 and module2 that are instantiated in module3.
Of course, in this very basic example, there is low interest for undefined Signal(). But I have designs where data come in the FPGA and are successively filtered by many modules. The width of the data changes at each module output and is dependent on module parameters and previous module data width.