I have written a “deglitch” component that I’d like to be “universal” : The component should be able to interface with boolean or bit-vector signals.
class deglitch():This text will be hidden
def __init__(self, deglitch_delay, initial_output=None):
self.deglitch_delay = deglitch_delay
self.initial_output = initial_output
@block
def inst(self, i_Clk, i_Data, o_Data):
DataSync = Signal(i_Data.val)
DataMemo = Signal(i_Data.val)
Counter = Signal(intbv(0, min=0, max=self.deglitch_delay+1))
DataOut = Signal(o_Data.val)
@always_seq(posedge(i_Clk), reset=None)
def proc():
DataSync.next = i_Data
DataMemo.next = DataSync
if DataMemo != DataSync :
Counter.next = 0
else :
if Counter == self.deglitch_delay :
Counter.next = 0
else :
Counter.next = Counter + 1
if Counter == self.deglitch_delay-1 :
DataOut.next = DataMemo
#o_Data.next = DataMemo
@always_comb
def logic():
o_Data.next = DataOut
return proc, logic
My problem is with internal signals that need to adapt themselves to external signals : DataSync, DataMemo and DataOut type must be the same than i_Data and o_Data.
I tried many syntaxes and ended with “DataSync = Signal(i_Data.val)”.
This syntax works with simulation and VHDL conversion.
I’m not very comfortable with this syntax.
- Is this the right way of writing ?
- Using this syntax, I can’t specify an initial value for the output. Is there a workaround ?