It is my myhdl case, I want to use Python generate some data pattern , then put it into ROM
from myhdl import Signal, ResetSignal, modbv,intbv
from myhdl import block, always_seq, Signal, modbv ,always_comb
from myhdl import enum,toVerilog,toVHDL
from myhdl import always
def rom(clk,dout, addr,reset_n, CONTENT):
#clk = Signal(bool(0))
#reset_n = Signal(bool(0))
@always(clk.posedge,reset_n.negedge)
def regout():
if reset_n == 0 :
dout.next = 0
else :
dout.next=CONTENT[int(addr)]
return regout
romc=[]
for i in range(256): romc.append(i*2)
CONTENT = tuple(romc)
clk = Signal(bool(0))
reset_n = Signal(bool(0))
dout = Signal(intbv(0)[8:])
addr = Signal(intbv(0)[8:])
toVerilog(rom,clk, dout, addr,reset_n, CONTENT)
This is my test_rom.py myhdl code, it is for the test bech. but I find the monitor function always output the fixed number, it is not what I defined with Python
#it is test_rom.py
import random
from myhdl import block, instance, Signal, intbv, delay,ResetSignal,always
from myhdl import *
from rom import rom
random.seed(5)
randrange = random.randrange
@block
def test_rom():
clk = Signal(bool(0))
reset_n = ResetSignal(0,active = 0, async= True)
dout=Signal(intbv(0)[8:])
addr=Signal(intbv(1)[8:])
#CONTENT=Signal(intbv(1)[8:])
#dout, addr= [Signal(intbv(1)[8:]) for i in range(2)]
romc=[]
for i in range(125):
romc.append(2*i)
CONTENT = tuple(romc)
print(CONTENT)
HALF_PERIOD = delay(5)
#DUT instance
rom_1 = rom(clk, dout, addr, reset_n,CONTENT)
@always(HALF_PERIOD)
def clockGen():
clk.next = not clk
@instance
def stimulus():
reset_n.next = 1
delay(20)
reset_n.next = 0
delay(20)
reset_n.next = 1
for i in range(200):
addr.next= randrange(256)
yield delay(10)
raise StopSimulation()
#monitor likes signalTAP
@instance
def monitor():
print("clock addr dout")
yield reset_n.posedge
while 1:
yield clk.posedge
yield delay(10)
print(" %s %s %s"%(int(clk),int(addr),dout))
return clockGen, stimulus,monitor
tb = test_rom()
tb.config_sim(trace=True)
tb.run_sim()
I have the following question: rom.py, I list it , test_rom.py , I list it, but I find the monitor output the ROM value is 0, what is my issue?
I put the data “2*i” into address “i” ,
D:\Tools\Python_tools\Python_examples\Python_examples\myHDL\rom\rom.py:40: UserWarning:
toVerilog(): Deprecated usage: See http://dev.myhdl.org/meps/mep-114.html
toVerilog(rom,clk, dout, addr,reset_n, CONTENT)
(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72, 74, 76, 78, 80, 82, 84, 86, 88, 90, 92, 94, 96, 98, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 142, 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, 166, 168, 170, 172, 174, 176, 178, 180, 182, 184, 186, 188, 190, 192, 194, 196, 198, 200, 202, 204, 206, 208, 210, 212, 214, 216, 218, 220, 222, 224, 226, 228, 230, 232, 234, 236, 238, 240, 242, 244, 246, 248)
clock addr dout
0 183 00
0 14 00
0 238 00
0 127 00
0 26 00
0 80 00
0 57 00
0 190 00
0 240 00
0 126 00
0 194 00
0 52 00
0 127 00
0 6 00
0 110 00
0 208 00
0 143 00
0 93 00
0 199 00
0 81 00
0 36 00
0 71 00
0 227 00
0 64 00
0 67 00
0 0 00
0 2 00
0 107 00
0 110 00
0 84 00
0 85 00
0 148 00
0 160 00
0 101 00
0 104 00
0 93 00
0 100 00
0 196 00
0 152 00
0 11 00
0 184 00
0 212 00
0 84 00
0 74 00
0 135 00
0 33 00
0 169 00
0 154 00
0 1 00
0 173 00
0 33 00
0 158 00
0 181 00
0 156 00
0 246 00
0 161 00
0 94 00
0 246 00
0 241 00
0 90 00
0 29 00
0 131 00
0 11 00
0 183 00
0 206 00
0 9 00
0 214 00
0 187 00
0 192 00
0 4 00
0 231 00
0 23 00
0 92 00
0 100 00
0 60 00
0 125 00
0 236 00
0 176 00
0 181 00
0 128 00
0 236 00
0 55 00
0 188 00
0 151 00
0 18 00
0 221 00
0 46 00
0 106 00
0 174 00
0 185 00
0 75 00
0 174 00
0 141 00
0 47 00
0 159 00
0 162 00
0 156 00
0 90 00
0 40 00
0 76 00
0 158 00
0 247 00
0 82 00
0 24 00
0 41 00
0 207 00
0 16 00
0 121 00
0 176 00
0 128 00
0 233 00
0 215 00
0 74 00
0 28 00
0 16 00
0 252 00
0 171 00
0 106 00
0 66 00
0 67 00
0 211 00
0 54 00
0 86 00
0 222 00
0 190 00
0 76 00
0 30 00
0 215 00
0 150 00
0 72 00
0 232 00
0 86 00
0 232 00
0 249 00
0 162 00
0 245 00
0 140 00
0 149 00
0 240 00
0 206 00
0 75 00
0 57 00
0 193 00
0 91 00
0 255 00
0 173 00
0 92 00
0 45 00
0 251 00
0 139 00
0 184 00
0 32 00
0 182 00
0 17 00
0 156 00
0 186 00
0 143 00
0 248 00
0 135 00
0 150 00
0 174 00
0 91 00
0 5 00
0 242 00
0 128 00
0 166 00
0 140 00