Is there a recommended MyHDL way to create a group of Signals?
In Python, I can declare a bunch of empty lists as:
a,b,c = ,,
a,b,c = *16,*8,[0,1,2]
Is there a more concise way in Python to declare a bunch of lists?
(I have also used list comprehensions, and dedicated classes to do it, and am just looking for a more terse way to do it.)
In Verilog I might do something like:
wire [31:0] a, b, c, d, e;
input [7:0] in1, in2 , etc.
In C++, I might model this using instances of a class Wire like:
Wire32 a, b, c;
In Python, if I were to use a class approach, one approach might be:
a = Wire32() b = Wire32() c = Wire32()
which seems a bit verbose to me. It gets even more complex when passing through MyHDL blocks. Still, I’m hoping this might be a reasonable simplification of the use case that might lead to relevant creative solutions.
My current solution is:
a,b,c = [Wire(32) for i in range(3) ]
I do not like a couple things about this solution:
1. I have to count the number of elements which is cumbersome and error-prone 2. The definition is after the list which is unfamiliar to the "customer" who will likely be a hw engineer familiar with Verilog
(This is a duplicate of a Stack Overflow question that is currently unanswered: python - Is there a more terse way to create a group of empty lists? - Stack Overflow )
I also found some information on creating MyHDL “Structures” of signals which could be a solution, but still having trouble wrapping my arms around it.
Here is an example of a post on interfaces that may lead to a good solution:
I’m sure there are other ways of creating classes to try create complex types, and then overload the operators, etc. for readability.
As always, thank you for your help as I try to learn the best practices in MyHDL!