Using lists of signals in myhdl


I am new here, and i am trying to use list of signals as the following :

memory = [Signal(intbv(0)[32:0]) for i in range(32)]

however i am having an issuse while converting to verilog as follows :

   'Name' object has no attribute 'value'

is here a simple way to implement that list and still be able to convert to verilog ?

best regards.

How/where is the list used ? In top level ports ?

A simple excerpt of code would be useful.

If you are trying to model a memory then your list of signals should be at your block scope. You also need to have a process to manage accessing your memory storage.

To get correct inference, you also need to have a set signals as ports, such as address, data, we, …

As @DrPi said, to give you more hints you need to share more code so that we understand what you are trying to do.