List of signals as a port is not supported : mem

Support
1

Hello,
I am currently working on a myhdl project (link here), and am facing a problem while converting a myhdl module to VHDL. I am a beginner in myhdl, and I don’t know what i am doing wrong: I receive a List of signals as a port is not supported: mem ConvertionError on the bram.py module.
Shouldn’t a memory module be represented as a list of signal? If not, how should I do it for it to be instantiable?

As a side question: Do I have to store the memory inside the block MemController (I actually want to have multiple reading heads in the future, for the same memory…)? If so, how should I do it?

Any help will be appreciated!

2

It’s working now,
passing the memory as an argument to the @block constructor means mapping all its bits to a port, which isn’t possible in Verilog and thus isn’t implemented for translation to either HDL. The fix was to make the list of signals - mem - a local definition, thus no mapping to port is required (and the generated VHDL is pretty close to a classic implementation of a Block-RAM).