MyHDL synthesis support / jupyosys

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Hi there,

I’ve been integrating a so far experimental yosys backend into MyHDL that directly creates synthesizeable module hierarchies without the transfer through V* languages.
It’s now at a stage where you can get simple designs spinning and verified (using post-map Co-Simulation of generated Verilog).
To make this easy to play with, it’s packed into a Jupyter notebook powered virtual machine that you can run as a binder or locally. It’s found here:

https://github.com/hackfin/myhdl/tree/jupyosys

(the Binder button will start the VM on mybinder)

In short, you can, out of the browser:

  • Co-Simulate MyHDL units against synthesized Verilog
  • Display waveforms and RTL elements
  • Synthesize for a ECP5 target (for now)
  • Program your FPGA board (when running as a local container on linux)
  • Run automated tests

Progress updates and some details on the project are here:

Examples/howtos/exercises are checked out inside the Binder from a secondary playground.
Any enhancements, bug reports or more use cases are of course welcome (i.e. feel free to submit your notebooks that [don’t] work)

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As a follow up: This project is going to be buried in favor of a next generation ‘kernel’ approach.
While serving some educational purpose, it turned out to cause more maintenance work and exposed a lot more limitations than expected, apart from the political issues (A future for the MyHDL community? - #77 by josyb)

So all new development will be going into the IRL based (intermediate representation language) kernel that is digesting myHDL syntax (up to some point). Entry page (Jupyter Notebooks as the above) and more info:

This is still regarded as possible future music and not intended for MyHDL beginners.
Although a few larger legacy projects were ported and verified to simulate/synthesize through the yosys back ends, it may still be necessary to rely on a proper verification of the emitted VHDL models, so: primarely for educational use.

Unlike the above jupyosys branch, I’ve taken a different approach to play with the relatively new CXXRTL simulation yosys backend that generates loadable DLL from RTL primitives. That one is again driven from a myHDL style test bench as usual, so several mapping stages can be co-verified in a more efficient way than going through verilog-based co-simulation - provided that CXXRTL path can be trusted (which seems so for synchronous designs).