Modelling wired-or (wired-and) bus behaviour

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1

Apologies if this is an obvious question - I’m a noob. Does MyHDL have any direct support for wired-or or wired-and bus behaviour, as used in e.g. I2C, CAN. If so, can you point me at an example?

2

MyHDL supports TriState signals, which you use as opendrain or opensouce … like we do in VHDL.
Maybe this: a simple tristate pin example in MyHDL · GitHub can set you on your way.

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Hi josyb, thanks for replying. I think the TristateSignal implementation is close, but doesn’t quite do what I’m looking for. In the examples I gave, both I2C and CAN allow for arbitration between multiple devices attempting to transmit at the same time (this is specified for I2C but isn’t common usage). A device which is transmitting the dominant state (0) while the other is transmitting the recessive state (1) wins. The TristateSignal implementation only allows a single driver (at most) to be active and gives a warning and resets the output state if multiple drivers are active. Having looked at TristateSignal my solution may be to produce something like it but with a different resolution method, thus:

    def _resolve(self):
        next = 1
        for d in self._drivers:
            if d.next == 0:
                next = 0
        self._next = next

I would prefer to use some inbuilt feature of MyHDL to cover this but maybe there isn’t one. What do you think?

I should add that I don’t expect to synthesize this. It’s just for simulation.

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I think I get it: you want to simulate the external wired-and bus? I have no good idea on how to do this in MyHDL or even if this is possible. Now I must confess that I never use MyHDL tristate pins; I always have an SignalOut and a SignalIn and do the open-drain in the top-level VHDL file ( as: SCl <= ‘0’ when SClOut = ‘0’ else ‘Z’; and SClIn <= SCl;) Making/simulating a bus is simple enough: AND-ing all xxxOut signals together and feed the single output back to all xxxIn pins.

5

Exactly. I think my approach will work, but your suggestion is good. I realised belatedly that the details of _Tristate and _TristateSignal differ, but the basic approach for the resolution method applies to both. Thanks for your help.