Multi-bit latch

Support
1

I’m new to MyHDL and trying to implement a simple design as a learning exercise. I am following the latch design in the examples but when I attempt to make it 8-bits wide (like a 74373), I have troubles. Are there any examples of multi-bit latches available?

2

Is this the latch example you are talking about:

from myhdl import *

def latch(q, d, g):

    @always_comb
    def logic():
        if g == 1:
            q.next = d

    return logic

I assume you only want one control signal, so this example should work for you as long as you use 8 bit wide Signals for the input d and the output q.

You do this outside the latch by defining the signals you will pass to d and q like

latch_input = Signal(intbv(0)[8:])
latch_output = Signal(intbv(0)[8:])
latch_gate = Signal(bool(0))

latch_instance = latch(latch_input, latch_output, latch_gate)

the challenge becomes then accessing the individual bits of the latched signals, you should be able to use ShadowSignals for that: http://dev.myhdl.org/meps/mep-105.html

3

Thank you! I’m starting to get use to the idea that the signal size can be specified outside the design. Very nice feature.

4

Not necessarily, you only need to use ShadowSignals if you want to pass a slice as an input to another function

5

Of course you are right.

I was thinking more of the case where the user might have many separate bool type signals which they want to feed into this one single latch, in which case they could use ConcatSignal. I haven’t had cause to use either Shadow or Concat signal much yet.