I need counter 4-bit with up count and down count in myhdl and convert to verilog or vhdl.
please help me
To get help, you need to provide detailed information. Do you have a sample design to submit ?
#I wrote this program but I don’t know where I’m wrong
from myhdl import *
ACTIVE, INACTIVE = bool(0), bool(1)
DOWN,UP, stop, clk , q = [Signal(INACTIVE) for i in range(5)]
DirType = enum(‘UP’, ‘DOWN’)
def counter(DOWN,UP, stop, clk, q):
I/O pins: -------- clk : input free-running clock goDown : input signal to down (active-low switch) goUp : input signal to up (active-low switch) stop : input signal to stop counting (active-low switch) q : 4-bit counter output @instance def logic(): dir = DirType.__reduce__ run = False while True: yield clk.posedge # direction if UP == ACTIVE: dir = DirType.__init__ run = True elif DOWN == ACTIVE: dir = DirType.__reduce__ run = True # stop if stop == ACTIVE: run = False # counter action if run: if dir == DirType.__reduce: q.next = q-1 else : q.next = q+1 return logic
counter = counter(DOWN,UP, stop, clk, q)
And also this app:
from random import randrange
from myhdl import *
ACTIVE_LOW, INACTIVE_HIGH = 0, 1
def Inc(count, down, enable, clock, reset):
@always_seq(clock.posedge, reset=reset) def incLogic(): if enable: count.next = count+1 if down: count.next = count-1 return incLogic
m = 4
count = Signal(modbv(0)[m:])
down = Signal(bool(0))
enable = Signal(bool(0))
clock = Signal(bool(0))
reset = ResetSignal(0, active=0, isasync=True)
counter_verilog = inc(count, down, enable, clock, reset)
I want to count from (0000) to (1111)
with up count and down count
So what happens when you run it? I assume you’ve written some kind of test to exercise it?
Also, I suggest working a bit more on your code formatting on discourse, which is a little hard to read.
It generally does not convert to vhdl or verilog.
If you can, send me the counter code.
There are two adder designs with test code here https://rosettacode.org/wiki/Four_bit_adder#MyHDL perhaps you could base your work on one of these?