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Using lists of signals in myhdl
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2
|
619
|
February 10, 2021
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|
Type mismatch with earlier assignment:
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15
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749
|
February 5, 2021
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AssertionError: Unexpected callable
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8
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816
|
January 6, 2021
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Myhdl signed assignment fails at runtime
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4
|
567
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December 23, 2020
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Use VHDL library
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3
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862
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July 5, 2020
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List of signals as a port is not supported : mem
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1
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830
|
March 26, 2020
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Is implementing a classification algorithm possible w/ MyHDL?
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1
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773
|
March 25, 2020
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How to do signed operations on intbv
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3
|
807
|
March 18, 2020
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How can I implement this?
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2
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752
|
March 3, 2020
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Another MyHDL VHDL conversion bug
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13
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1460
|
October 17, 2019
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Mutiple traces/simulations in one run
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4
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1003
|
October 13, 2019
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How can I use lists of signals and still convert to verilog
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12
|
2072
|
September 18, 2019
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Conversion problem with shadow signal
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8
|
842
|
September 3, 2019
|
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Unexpected signal name in converted VHDL
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4
|
943
|
August 1, 2019
|
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How to dynamically infer ports?
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6
|
995
|
August 1, 2019
|
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Large memory consumption
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13
|
1711
|
May 14, 2019
|
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Vendor specific instance simulation
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|
1
|
847
|
April 19, 2019
|
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Conversion naming issue
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|
8
|
1152
|
April 5, 2019
|
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Verilog conversion to write results to a file?
|
|
12
|
1122
|
April 4, 2019
|
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Don't care / unknown
|
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4
|
1100
|
March 28, 2019
|
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Function not converting, but deflated code does
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8
|
968
|
March 23, 2019
|
|
How to simulate for the ROM type design
|
|
17
|
1861
|
March 12, 2019
|
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'tuple' object has no attribute 'config_sim'
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1
|
903
|
February 25, 2019
|
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Changing testbench inputs during a simulation
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|
8
|
1089
|
February 13, 2019
|
|
Instantiating FPGA components
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|
7
|
2154
|
February 2, 2019
|
|
Combinational tree like accumulatioin
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|
6
|
1108
|
December 10, 2018
|
|
Cosimulation myhdl.vpi search path
|
|
2
|
3469
|
November 8, 2018
|
|
Using standart Python modules
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|
2
|
790
|
October 10, 2018
|
|
Verilog width expansion and reduction operator equivalence?
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|
2
|
1736
|
October 6, 2018
|
|
Invoke Verilog generate for Python list handling
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|
1
|
1268
|
October 1, 2018
|