The problem with simulation/conversion behavior differences is always present, even when not using vendor IP. This is because the converter and simulator are (partially) independent piece of code.
This is the reason why there is co-simulation.
When instantiating vendor IPs, you have to create a MyHDL model for simulation.Then, you have to use .vhdl_code or .verilog_code for conversion. Please see the associated documentation here : http://docs.myhdl.org/en/stable/manual/reference.html#user-defined-verilog-and-vhdl-code
Please note that your simulation model doesn’t need to be convertible. This means that for a FIFO, you can use a list with .append() and .pop().
I have written some Python code to automatically convert Xilinx unisim library to MyHDL. Please note that it has been written for MyHDL 0.8. I might update it for MyHDL 0.10 in the future. You can refer to it as an implementation example. It is here : https://bitbucket.org/nico-dev/myhdl_xilinx_unisim_lib
You can create a FIFO model in pure MyHDL and use it in simulation and conversion. This works perfectly. The vendor synthesizer detects a block of RAM and all logic around the RAM correctly. Even a dual clock FIFO can be modeled.
However, this doesn’t work with embedded FIFOs present in Xilinx chips.