I’m trying to use a Python-Verilog interface to simulate a CPLD (or rather, a web interface for a CPLD) that allows a user who enters the website to be able to enter Verilog code for that CPLD, compile it, and simulate it while being able to change the inputs as they would with the CPLD itself.
I understand cosimulation would be the way to go, since users would be writing in Verilog and I would be using Python MyHDL to write the test bench. However from what I’ve read about MyHDL, the inputs to the simulation are fixed, i.e. they can’t be changed outside of a static test bench design.
My goal is for users to change inputs to the CPLD on my website, and reflect those changes in the simulation while it is running. How would I achieve that in MyHDL?