Hello,

I want to create a (convertible) structure that will accumulate a list of signals in always_comb, here is a code that works perfectly fine (calc_elems is a list of signals, filled from 0 to in_size):

```
calc_elems_len = 2 * in_size - 1
@block
def add(z, x, y):
@always_comb
def logic():
z.next = x + y
return logic
add_inst = list()
for i in range(in_size, calc_elems_len):
a = 2 * i - 2 * in_size
b = a + 1
add_inst.append(add(calc_elems[i], calc_elems[a], calc_elems[b]))
```

I can use it in simulation and it converts into correct VHDL. But its not very nice to use, I would like to do something like this:

```
calc_elems_len = 2 * in_size - 1
for i in range(in_size, calc_elems_len):
a = 2 * i - 2 * in_size
b = a + 1
@always_comb
def add_me():
calc_elems[i].next = calc_elems[a] + calc_elems[b]
```

The problem is that I get:

`myhdl.AlwaysCombError: signal ({'calc_elems'}) used as inout in always_comb function argument`

Which is not true, because each signal in the list is used exactly in one direction in one always_comb. Unless list of signals is treated as a whole, which is wrong.

Is there a way to achieve this without the need to create an extra add block?