Don't care / unknown

Is there a way of assigning a variable a don’t care / unknown type in MyHDL?
For example, in verilog I’d write
wire [3:0]dontcare=4’bxxxx;

What are you trying to achieve ?

My current primary motivation is I like to assign invalid data don’t cares since it makes reading waveform diagrams easier. For example, in an AXI stream if valid is 0 I like to make data a don’t care vector. However, there are lots of other reasons you’d want don’t cares.

Here is a way to manage signals with an unknown value :

from myhdl import block, Signal, TristateSignal, intbv, always_seq

def dut(i_clk, i_din, i_en, o_dout):

    @always_seq(i_clk.posedge, None)
    def regout():
        if i_en :
   = i_din
        else :
   = None
    return regout

def simulate_dut():
    from myhdl import instance, always, delay, StopSimulation
    i_clk = Signal(bool(0))
    i_en  = Signal(bool(0))
    i_din  = Signal(intbv(0)[8:])
    o_dout = TristateSignal(intbv(0)[8:])    # Create Tri-state  signal
    dout = o_dout.driver()                   # Get a driver for the tri-state signal

    dut_inst = dut(i_clk, i_din, i_en, dout)

    def clk_gen(): = not i_clk

    def delay_clk(clk, dly) :
        for _ in range(dly) :
            yield clk.posedge
    def inputs_gen() :
        yield delay_clk(i_clk, 20) = True
        yield delay_clk(i_clk, 20) = False
        yield delay_clk(i_clk, 10) = 0xA5
        yield delay_clk(i_clk, 20) = True
        yield delay_clk(i_clk, 10) = 0x5A
        yield delay_clk(i_clk, 20) = False
        yield delay_clk(i_clk, 20)
        raise StopSimulation()
    return dut_inst, clk_gen, inputs_gen

def simulate():
    tb = simulate_dut()
    tb.config_sim(trace=True, timescale='1ns', directory=".", tracebackup=False)
if __name__ == "__main__" :

Simulation result :

Beware that high impedance signals are not supported for long time in modern FPGAs (except for I/O signals).

Thanks for the tip and example. I think this might supplement what I want.