I am implementing single cycle processor, RV32I ... i am facing issues in top module.. file named as " core.py "

In core.py i have merged all modules and it is the top module of my signle cycle core, when simulating it, it doesnt updates signals, why is this so i am not getting it please someone guide me.

here is the link of my repo, kindly check core.py file.

Congratulations, you have expended a lot of work, or translation here. I was also very reluctant to build tests for everything, but this can save much time, for example, see: Johnson Counter

You seem to have a problem inferring latches. Compare your DataMemory.py/.v with the RAM inference example at: Conversion examples — MyHDL 0.11 documentation and note the difference in the .v files of the memory declaration, particularly “wire” vs “reg”. Your “RegisterFile.py” likely has a similar problem.

I suspect that this problem also occurs elsewhere. Your design contains “@always_comb” 12 times, but only one each of “@always(clk.posedge)” and “@always(clk)”. This last probably needs “.posedge” adding.