I checked the FSM and found it inferred casez:
casez (state)
3’b??1: …
3’b?1?: …
3’b1??: …
This coding style is forbidden by us, since it will infer prioritize case(just like if-else), and casez will may generate bug if some signal really have value of Z.
I think system verilog already provide unique case and full case, how to generate such code?
Furthermore, can I define some rules to constraint the code generation to verilog?
Thanks.
Logan.