MyHDL

How to infer to unique case

I checked the FSM and found it inferred casez:
casez (state)
3’b??1: …
3’b?1?: …
3’b1??: …
This coding style is forbidden by us, since it will infer prioritize case(just like if-else), and casez will may generate bug if some signal really have value of Z.

I think system verilog already provide unique case and full case, how to generate such code?

Furthermore, can I define some rules to constraint the code generation to verilog?

Thanks.
Logan.

Dear Logan,

I agree that the casez is not suited. I have a PullRequest #357 to use the standard case instead.
But unfortunately we have to wait for it to be merged.

Best regards,
Josy