The conversion of my one-hot state machine design surprised me. Instead of expressing the cases as bitfields of all 0s but one 1, the cases are all don’t cares (?) but one 1.
... else begin casez (io1_trigger_state) 3'b??1: begin if ((io1_trigger_source && io1_gate_source)) begin trigger <= 1'b1; io1_trigger_state <= 3'b010; end end 3'b?1?: begin trigger <= 1'b0; io1_trigger_state <= 3'b100; end 3'b1??: begin if ((!io1_trigger_source)) begin io1_trigger_state <= 3'b001; end end default: begin io1_trigger_state <= 3'b001; end endcase end ...
I realize that the logic for this is simpler but it also can result in less deterministic behavior if an invalid state is somehow reached. Since all invalid states branch to whatever state is the best match instead of to the default state specified, the behavior is unpredictable and my default state clause is useless. I suspect this was a considered MyHDL implementation but I thought I would post it anyway.
Is this the intended behavior?