MyHDL

Design functions when the clock is inverted

I have a design that functions when my simulation stimulus contains

clock = Signal(False)    # works

but does not function when the simulation contains

clock = Signal(True)    # does not work

All clocking in the design is positive edge. Nothing else in the source files are changed. Since the MyHDL simulator is purely functional, what could cause such behavior? I don’t understand how this case could occur.

Hard to say without a code snippet showing the problem…

You have to look at the code that drives the clock signal; apparently this code does not start when the initial value of the clock signal is set to True. As @DrPi says: without the actual source code it is impossible to accurately pinpoint the issue.