Using a signal declared like this :
data = Signal(intbv(0)[4:]
I want to change only one bit of this signal in a process. For example :
@always_seq(posedge(i_Clk), reset=None) def regs_manager(): if ... : data.next = 0 else : data.next = 1
In simulation, I get the following error :
AttributeError: ‘bool’ object has no attribute ‘next’
Conversion to VHDL seems to give correct result.
Looks like this is a bug a bug. Right ?
Note : I use last github version of myhdl with @block decorator syntax