Currently, cosimulating verilog code requires a stub testbench. This is not a problem for modules generated by MyHDL, but it makes cosimulating arbitrary modules inconvenient. I think we can eliminate the need for the stub and automatically infer
from_myhdl from the interface of the module(In the vpi module).
This will require changing the interface of the current VPI module, but I’m willing to give this a shot. It seems like it shouldn’t be too hard.
The goals of the project:
- Cosim VPI module written in rust. The binary can be distributed with the next MyHDL release.
- Allow users to cosimulate with installed simulators using little to no boilerplate. See uhdl for inspiration.
- Interfacing with existing Verilog/VHDL modules should be dead simple, there is no need for the Cosimulation object to know the list of ports. See cocotb for inspiration.