Here is a dump of GSoC ideas I would like to mentor. Looking for feedback before I put them on the ideas page.
FIRRTL conversion support
Add support for converting MyHDL block’s to FIRRTL.
Whether we like it or not, FIRRTL is the future. Since it is backed by the Berkley folks, a bunch of tools and libraries for FIRRTL will pop up. In the future, we can drop support for conversion to Verilog and VHDL and use FIRRTL converters instead.
Students who want to work on this project will need to go through the FIRRTL spec and identify potential caveats and limitations of converting MyHDL to FIRRTL.
Improving cosimulation
This project will entail writing a new VPI module in Rust which will allow more user friendly cosimulation.
More info: Making cosimulation more user friendly
Hi, I’m interested in expanding the idea FIRRTL conversion support for 2017 GSoC project. I have some python and VHDL/Verilog experiences before but I’m not familiar with MyHDL or FIRRTL at all. I’m now trying to catch up and I wish to have more suggestions. I also expect to have more discussions with you about converting this idea into an application proposal.
FIRRTL may be interesting, but IMHO it is not there yet .e.g. there is no VHDL translator. A ‘verbatim’ search on Google for ‘FIRRTL VHDL translate’ only produced 5 hits, so I guess there is nothing planned there.
From the gsoc manual project idea can be (but not limited to):
low-hanging fruit
risky/exploratory
fun/peripheral
core development
infrastructure/automation
The FIRRTL would be a exploratory type project, at this point in time I don’t have an opinion if it is a good or bad investment (as in student and mentor time), seems reasonable to investigate as a gsoc.
The other proposed projects (some need write-ups asap) would be fixbv which would be core development and all things waveforms would be peripheral.
I don’t have a strong opinion which one would be more useful but what is true, is that a mentor is needed and a description. @jck offer to mentor FIRRTL and @hgomersall offer to mentor RedBaron, the students can work with the possible mentors to create a proposal. Then we can review the proposals and determine which would be more useful.
Also, students will need to create a PR before they can be accepted, this is a requirement of PSF.
@cfelton@josyb Thank you for your comments, they are helpful for getting started.
For my previously interested idea, I’ve just read the FIRRTL specification roughly and gained some basic knowledge. I’ve been working on the MyHDL Manual to get more familiar with MyHDL, but there is still no inspiration now.
@cfelton Since I know the Fixed-point Compiler idea is among the project ideas, do you have any further suggestion if I give a try on this idea now? Maybe I should write some prototype and create a pull-request immediately?
@max I have had some other students inquire about the fixbv project but no one has written a proposal yet - feel free to investigate the fixbv project as well. The fixbv project involves creating the ast parsers and conversion/compiler, see the fixbv MEP listed in the myhdl gsoc page
@cfelton
I woke up this morning with the idea of supporting the MyHDL FIRRTL backend idea, and considered to write a VHDL converter later.
But I studied the FIRRTL spec (again) in more detail and now understand why there is no VHDL converter in the works, or very probably never will be. E.g. FIRRTL lacks the VHDL constructs enum, case, … and as a consequence the VHDL output would be no richer than the Verilog output.
So dropping VHDL output from MyHDL later definitely will be a no-no.
I’d really/rather like to see a student working on a RedBaron based IR first.
It looks like we need to think and discuss more about FIRRTL. Keeping that in mind, it might not be the best use of student time right now.
On the other hand, the cosimulation could be immediately useful and I already have a clear idea of what needs to be done. I’ll do a write up later today. Short version is that it would make integrating external modules into simulations effortless.
Perhaps we should try to steer students to that project instead?
EDIT: I mean for the project which I will be mentoring. I’m assuming that Chris will be mentoring a fixbv project.
@cfelton Honestly speaking, contributing to the MyHDL is the most exciting and interesting thing to me. According to your discussions, the cosimulation is a chance I should never miss. As to rust, I’m not familiar with it unfortunately.
@jck I’d love to try my best and investigate the cosimulation as a GSoC project. I plan to go on learning MyHDL now and I look forward to seeing your further description (will it be posted as a MEP?)
@max you will want to start working on your proposal, the application period opens tomorrow and you will have almost two weeks to complete it, don’t wait till the end the sooner the better. Also, the sooner you get a draft of the proposal the sooner we can review it. In your investigation review the VPI modules, @jck can provide additional info.
Hello . I am interested to work on the project idea of All things waveform viewing in MyHdl using matplotlib,python. I have experience in python and matplotlib. Which I think will be an advantage for me. But I am complete new to MyHdl. Presently I am going through and all the documentations of MyHdl. I need some guidance in this project. I want suggestions from my mentors to guide me in this so that I can be able to contribute towards this project.
The proposal was finished in such a hurry that some parts of it must be disasters. I do wish I can make up.
As you mention PR, I believe you are talking about the code sample required to be submitted as pull request, which I have not accomplished yet.
I should have asked much earlier but I hope it’s not too late now: What constitutes an appropriate sample/patch in your opinion? Do you have any more specific requirements?
