Read http://dev.myhdl.org/gsoc/gsoc_2017.html
Then, introduce yourself here. Tell us about your background and interests in compilers/code generation/digital design.
After creating a draft proposal, notify the potential mentors on gitter or discourse if you would like early feedback on your proposal.
I updated the 2017 project ideas. Students can review the project ideas and then start a conversation in this thread to discuss myhdl, the community, and the projects.
My name is Alvi and I’m a GSoC hopeful interested in getting involved with the MyHDL package. I’m a Junior at the University of Toronto in Canada majoring in Computer Science, and Neuroscience.
Among the large catalogue of the usual theoretical/practical courses most students take in college, I find that I enjoy myself most working with program correctness, performing algorithm analysis, building small tools in Verilog, and above all designing deterministic and non-deterministic Finite State Automata. Given that, I naturally gravitated towards MyHDL, specifically working on state-machine improvements.
Concerning my experience, I have designed a number of simple utilities in Verilog for use on an Altera Cyclone V FPGA including simple counters, calculators, ALUs, and controllers. I was so captivated by the hardware that I ventured into making a small arcade-style game that I can output to my monitor. This turned into a fairly large project and I have recently uploaded to my Github page. My exposure to compilers has been fairly basic, as part of a particular software design course. I am currently delving deeper into that topic, as I’m in the process of working through the Python compiler package as even though it is removed from Python 3, it may help me to understand some inner workings of MyHDL. I am also halfway through the MyHDL manual and learning more about its utilization. I can tell however that I will need some assistance hashing out my exact project and more specifics. As of now, I’m looking into inlined methods vs. combinatorial only functions when it comes to state-machine improvements, thanks to some much appreciated headings from @cfelton .
I will be much more available this summer than I am currently, averaging between 35-45 hours per work-week. My only other commitment will be as a volunteer for a non-profit here in Toronto. Under a grant from the Canadian Internet Registration Authority (CIRA), we teach marginalized groups and individuals in Toronto about FOSS and how to use GNU/Linux as an OS to bridge the digital divide by providing them the knowledge and technology to do so. That would keep me busy during weekends.
I look forward to a very productive summer and to work with MyHDL! Cheers.
Hello. I am K Sanjay Reddy from India. I am very much interested in MyHdl projects especially the All things waveform viewing vor MyHDL using matplotlib. I think my experience in python and matplotlib will help me to contribute towards this project. I request dear mentors to provide me more details about this particular project.
Hi, everyone! I’m Zhengfu Li (and you can call me Max) from China. I graduated in 2016 and I will begin my graduate study in fall, 2017.
From undergraduate training, I gained my hardware design experiences, which I thought I would never have the chance to use them in the future as I worked as a backend/python engineer after graduation. Python is charming and I do enjoy using it to practice in LeetCode as well. Naturally, I was attracted by the MyHDL project and decided to contribute to it in GSoC at first sight.
As I’m in the middle of two programs and I already resigned, I have enough time and effort to prepare right now. To emphasize, discussions with mentors in previous post encourage me a lot, and now I’m in a good process towards my proposal. @jck I look forward to working and communicating with my mentor on the co-simulation improvement idea, and there is no doubt that I’ll try my very best to do my job.