Currently, each time a python source file is converted to VHDL, signal declarations are in a different order.
I propose to sort signal declarations in generated VHDL to always get the same order.
The reason why is to be able to easily compare 2 generated files.
This is useful in various situations :
- Upgrading MyHDL : check that the output code is still the same.
- Comparing algorithms : compare generated files
- Working on a source file : compare generated file with previous version
- Other situations where 2 generated files have to be compared
The correction is very simple. Just add the two following lines at the beginning of _writeSigDecls() function in _toVHDL module :
siglist.sort(key=lambda x:x._name.lower()) memlist.sort(key=lambda x:x.name.lower())
I guess the same could be done in _toVerilog module but I don’t use Verilog.
What do you think of this ?