Can somebody explain how to use TristateSignal’s and create verilog that can be synthesised?
If I understand the documentation correctly, this needs to be done like this:
(BUS is the “bus”, io1 and io2 are two signals driving the bus).
BUS = TristateSignal(intbv(0)[1:])
toVerilog(top, clk, systemreset, BUS)
io1 = BUS.driver()
io2 = BUS.driver()
io1.next = 0
io2.next = None
However, looking at the generated verilog code, I have this:
module top (
output [0:0] BUS;
wire [0:0] BUS;
reg [0:0] io2;
reg [0:0] io1;
assign BUS = io1;
assign BUS = io2;
And this does not synthesise "(“net has multiple drivers”) according arachne-pnr.
So how do you write this myhdl code that is does synthethise.
As far as I understand this, a “TriStateSignal” is in essence a combinatory logic-block that produces the correct output, based on the input of the “driver” modules.
So am I correct to assume that, when you convert this into verilog, you still need to implement that block yourself in verilog ?
Or am I missing something here?
The actual use of this code is to learn how to access the SRAM module on an olimex ice40HX8K-EVK board where two modules (the top block to program the SRAM and a “vga” block that reads the SRAM) need to access the databus and addressbus of the memory.