VHDL conversion - missing constant

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@meowsqueak
Basically, MyHDL “runs” the code when simulating but “interpret” it when converting. Also, there is a converter for VHDL and a converter for VERILOG.

This means you can simulate code than can’t be converted.
For example, a FIFO can be modelled with a simple list. You can simulate your design with this model but you can’t convert it.
This is cool because you can simulate everything you want, but you have to be careful when designing “convertible” modules.

Your assumption that you will convert to verilog and VHDL to check conversion is not good. As I said, verilog converter and VHDL converter are separate. There might be a bug in one converter that is not present in the other. There might be functionalities supported in one converter that are not supported in the other. On my side I have enhanced the VHDL converter to suit my needs but not the verilog one since I don’t use it and I don’t have enough verilog knowledge.

There is no “Constant” type in MyHDL for now. It has been discussed to add this functionality but it is not implemented yet.

One workaround is :

def Constant(data_type):
    """ Pseudo constant (a signal is writable) """
    const = Signal(data_type)
    const.driven = True         # Remove warning
    return const


PATTERN_SOS = intbv("101010001110111011100010101") 

@block def Blink(clk, clk_en, led): 
    pattern = Constant(PATTERN_SOS)
    counter = Signal(modbv(0, min=0, max=32))
...